A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

A non-volatile memory device and method of making the same is provided. The memory device includes a first electrode, a first hard mask on the first electrode, a second electrode on the first hard mask, a second hard mask on the second electrode, and a third electrode on the second hard mask. A switching layer is over the electrode stack and the switching layer has a first portion conformal to the side surfaces of the electrode stack.

There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M.sub.8XY.sub.6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M.sub.8XY.sub.6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal. The invention is based on the three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of the source-drain resistance with respect to the control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.

A semiconductor structure for a vertical phase change memory cell that includes a bottom electrode on a portion of a semiconductor substrate and a pair of vertical phase change bridge elements that are each on a portion of the bottom electrode. The semiconductor structure for the vertical phase change memory cell includes a dielectric material separating the pair of vertical phase change bridge elements and a top electrode over the pair of vertical phase change bridge elements.

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device, and at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion. The resistive memory device includes terminals configured to couple the active region to associated electrical contacts.