Provided are a chalcogenide material, and a device and a memory device each including the same. The chalcogenide material may include: germanium (Ge) as a first component; arsenic (As) as a second component; at least one element selected from selenium (Se) and tellurium (Te) as a third component; and at least one element selected from the elements of Groups 2, 16, and 17 of the periodic table as a fourth component, wherein a content of the first component may be from 5 at % to 30 at %, a content of the second component may be from 20 at % to 40 at %, a content of the third component may be from 25 at % to 75 at %, and a content of the fourth component may be from 0.5 at % to 5 at %.

A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

A storage device includes a first electrode, a second electrode, and a storage layer. The second electrode is disposed to oppose the first electrode. The storage layer is provided between the first electrode and the second electrode, and includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), transition metal, and oxygen. The storage layer has a non-linear resistance characteristic, and the storage layer is caused to be in a low-resistance state by setting an application voltage to be equal to or higher than a predetermined threshold voltage and is caused to be in a high-resistance state by setting the application voltage to be lower than the predetermined threshold voltage to thereby have a rectification characteristic.

A three-dimensional memory device includes: a plurality of word line groups including a plurality of word lines; a plurality of bit line groups extending in a vertical direction and including a plurality of bit lines spaced apart from the plurality of word lines; a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines and including a switching component and a variable resistance memory component; a plurality of global bit line groups connected to the plurality of bit line groups, wherein each of the plurality of global bit line groups includes a plurality of global bit lines electrically connected to a plurality of bit lines included in one bit line group, respectively; and a pad structure including a plurality of connection units and a plurality of pad layers, wherein the plurality of connection units are connected to the plurality of word line groups.

Silicon compounds may be represented by the following formula:

##STR00001##

Each of R.sup.a, R.sup.b, and R.sup.c may be a hydrogen atom, a halogen atom, a C1-C7 alkyl group, an amino group, a C1-C7 alkyl amino group, or a C1-C7 alkoxy group, R.sup.d may be a C1-C7 alkyl group, a C1-C7 alkyl amino group, or a silyl group represented by a formula of *—Si(X.sup.1)(X.sup.2)(X.sup.3). Each of X.sup.1, X.sup.2, and X.sup.3 may be a hydrogen atom, a halogen atom, a C1-C7 alkyl group, an amino group, a C1-C7 alkyl amino group, or a C1-C7 alkoxy group, and * is a bonding site. In some embodiments, when R.sup.b is the C1-C7 alkyl amino group and R.sup.d is the C1-C7 alkyl group, R.sup.b may be connected to R.sup.d to form a ring. To manufacture an integrated circuit (IC) device, a silicon-containing film may be formed on a substrate using the silicon compound of the formula provided above.

Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The bulk region may extend between the first electrode and the sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may separate the bulk region from the second electrode.

Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in planar structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. A conductive path between the first electrode and the second electrode may extend in a direction away from a plane defined by a substrate. The self-selecting storage element may include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. The bulk region and sidewall region may extend between the first electrode and the second electrode and in the direction away from the plane defined by the substrate.

Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.

Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.