Disclosed is a synaptic device, a reservoir computing device using the synaptic device, and a reservoir computing method using the reservoir computing device. The synaptic device includes a substrate and a plurality of units cells on the substrate, wherein the unit cells each include a channel layer and a first electrode and second electrode intersecting the channel layer, wherein the first electrode and the second electrode are spaced apart from each other, and define a gap region exposing a portion of the channel layer, and the channel layer includes a 2-dimensional semiconductor material or a 2-dimensional ferroelectric material.

A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Provided are a chalcogenide-based material, and a switching element and a memory device that include the same. The chalcogenide-based material includes: a chalcogenide material and a dopant. The chalcogenide material includes Ge, Sb, and Se. The dopant includes at least one metal or metalloid element selected from In, Al, Sr, and Si, an oxide of the metal or metalloid element, or a nitride of the metal or metalloid element.

In one embodiment, a method of manufacturing a semiconductor device includes forming a first layer including a metal element on a substrate, and processing the first layer by dry etching. The method further includes removing a second layer formed on a lateral face of the first layer by wet etching, after processing the first layer, and forming a first film on the lateral face of the first layer by processing the lateral face of the first layer with a liquid, after removing the second layer. Furthermore, the substrate is not exposed to ambient air, after removing the second layer and before forming the first film.

A semiconductor storage device including a phase change memory film having a composition containing at least Ge, Sb, Te, and Se, and containing Se as a design composition ratio to Te in a composition ratio showing a phase change memory property with at least three elements Ge, Sb, and Te. The composition ratio of Se is 33.6 atom % or less.

A method of forming bottom electrodes in a resistive memory device, can include: depositing a bottom insulator on a substrate ILD; forming vias in the substrate by patterning and etching holes in the bottom insulator and the substrate ILD; filling the holes with a via metal to form a flat via surface; depositing a bottom electrode thin film and a top insulator; defining the bottom electrode; etching the top insulator, the bottom electrode thin film, and the bottom insulator; depositing a cell plate layer having a switching layer, an anode layer, and a cap layer; patterning the cell plate layer by depositing and patterning a cell plate hard mask layer, and then etching the cell plate layer; encapsulating the cell plate layer; and forming electrical contact to the cell plate layer.

Provided are a semiconductor device and a semiconductor apparatus. The semiconductor device may include a first electrode; a second electrode spaced apart from the first electrode; and a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer. In the semiconductor device, by doping the metal oxide, an off-current value (leakage current value) of the selection device layer may be reduced, and static switching characteristics may be implemented.

A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

A memory cell array of the present disclosure includes a plurality of memory cells 11 arranged in a first direction and a second direction different from the first direction. Each of the memory cells 11 includes a resistance-variable nonvolatile memory element and a selection transistor TR electrically connected to the nonvolatile memory element. The selection transistor TR is formed in an active region 80 provided in a semiconductor layer 60. At least a part of the active region 80 is in contact with an element isolation region 81 provided in the semiconductor layer 60. A surface of the element isolation region 81 is located at a position lower than a surface of the active region 80.

A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 μs to about 54 μs.