A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.

A three-dimensional memory device includes: a plurality of word line groups including a plurality of word lines; a plurality of bit line groups extending in a vertical direction and including a plurality of bit lines spaced apart from the plurality of word lines; a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines and including a switching component and a variable resistance memory component; a plurality of global bit line groups connected to the plurality of bit line groups, wherein each of the plurality of global bit line groups includes a plurality of global bit lines electrically connected to a plurality of bit lines included in one bit line group, respectively; and a pad structure including a plurality of connection units and a plurality of pad layers, wherein the plurality of connection units are connected to the plurality of word line groups.

The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide.

A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.

Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.

A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

This method comprises the following steps: a) providing a stack successively comprising: a substrate; a first electrode; a first dielectric layer, having a first electrical strength; a second metal electrode; a second dielectric layer, having a second dielectric strength that is strictly less than the first dielectric strength; a third electrode; the first dielectric layer and the second electrode having a first interface, the second dielectric layer and the second electrode having a second interface; b) etching the stack by bombardment with electrically charged species, so as to define resistive memory cells; the bombardment of step b) being adapted so that electrically charged species accumulate at the first and second interfaces of each resistive memory cell, so as to generate an electric field that is strictly less than the first electrical strength and is strictly greater than the second dielectric strength.

A memory device includes a memory cell and a first select transistor. The memory cell includes a variable resistance memory region, a first semiconductor layer being in contact with the variable resistance memory region, a first insulating layer being in contact with the first semiconductor layer, and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes a second semiconductor layer, a second insulating layer being in contact with the second semiconductor layer, and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.