An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

The present invention disclosures a RRAM cell structure, comprising a first transistor and a second transistor which are connected in parallel and commonly connected to a resistive switching device; wherein, the first transistor is set with a first gate, a first source and a first drain, a first control signal is applied to the first gate, and a first source signal is applied to the first source; the second transistor is set with a second gate, a second source and a second drain, a second control signal is applied to the second gate, and a second source signal is applied to the second source; the first drain is connected with the second drain, which are commonly connected to one terminal of the resistive switching device, and a bit signal is applied to another terminal of the resistive switching device. The present invention uses cell area of a traditional 1T1R to manufacture a 2T1R cell structure, which can take into account various operating voltage requirements of the resistive switching device simultaneously, so as to significantly improve cell performances thereof.

Provided is a nonvolatile memory device including a lower electrode on a substrate, an upper electrode on the lower electrode, a tunnel barrier pattern between the lower electrode and the upper electrode, and a fixed charge pattern in contact with the lower electrode and spaced apart from the tunnel barrier pattern with the lower electrode therebetween. The tunnel barrier pattern includes an anti-ferroelectric material. The lower electrode includes a first material. The upper electrode includes a second material. The first material and the second material have different work functions.

The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer, a magnetic reference layer, and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes bottom and top electrodes, first and third volatile switching layers interposed between the bottom and top electrodes, and a second volatile switching layer interposed between the first and third volatile switching layers. The bottom and top electrodes each independently include one of titanium nitride or iridium. The first and third volatile switching layers each include tantalum oxide and silver. The second volatile switching layer includes hafnium oxide and has a higher electrical resistance than the first and third volatile switching layers.

A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

A resistive memory device is provided. The resistive memory device comprises a first electrode and a resistive layer over the first electrode, the resistive layer having a sidewall. A second electrode is over the resistive layer. An insulating liner is formed on the sidewall of the resistive layer. The insulating liner comprises two layers of different dielectric materials.

A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed.

Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.

Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a switching oxide stack formed on the bottom electrode. The switching oxide stack includes one or more base oxide layers and one or more discontinuous oxide layers alternately stacked; An apparatus further includes a top electrode formed on the switching oxide stack. The base oxide layer includes TaO.sub.x, HfO.sub.x, TiO.sub.x, ZrO.sub.x, or a combination thereof. The discontinuous oxide layer includes Al.sub.2O.sub.3, SiO.sub.2, Si.sub.3N.sub.4, Y.sub.2O.sub.3, Gd.sub.2O.sub.3, Sm.sub.2O.sub.3, CeO.sub.2, Er.sub.2O.sub.3, or the combination thereof.