A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NH.sub.3 gases. The dry chemical gas removal process utilizing HF and NH.sub.3 gases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products.

A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

Disclosed are electrochemically tunable metamaterials which are capable of complete reversibility such that the metamaterial itself can physically disappear (out of the active region) and reappear later, in a controllable manner. Some variations provide an electrochemically tunable, solid-state metamaterial-based device comprising a plurality of metamaterial unit cells, wherein each of the metamaterial unit cells comprises: an ion conductor containing mobile metal ions; a first electrode in contact with the ion conductor, wherein the first electrode is contained in a metasurface negative space disposed on the ion conductor; a second electrode in contact with the ion conductor, wherein the second electrode is electrically isolated from the first electrode; and a metal-containing region containing one or more metals, wherein the metal-containing region is contained within a metasurface positive space disposed on the ion conductor.

A memory device includes a transistor, a memory cell, and an interconnect layer. The transistor includes a bottom source/drain portion, a channel portion, and a top source/drain portion stacked from bottom to top and a gate structure surrounding the channel portion. The memory cell includes a nanowire bottom electrode, a first dielectric layer, a second dielectric layer, and a top electrode. The first dielectric layer laterally surrounds the nanowire bottom electrode. The second dielectric layer is over the nanowire bottom electrode and the first dielectric layer. The second dielectric layer is in contact with a top surface of the nanowire bottom electrode and a sidewall of the first dielectric layer. The top electrode covers the second dielectric layer. The interconnect layer is over the transistor and the memory cell to interconnect the transistor and the memory cell.

A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.

A variable resistance memory device includes: a supporting layer including an insulating material; a variable resistance layer on the supporting layer and including a first layer including a metal oxide and metal nanoparticles, the variable resistance layer including a second layer on the first layer and including an oxide; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a gate electrode on the gate insulating layer. The metal nanoparticles in the variable resistance layer include a first metal capable of combining with oxygen ions of the metal oxide, thereby increasing oxygen vacancies.

A method for producing a resistive memory cell from a stack of layers having a metal-oxide layer interleaved between first and second electrodes includes forming, within one from among the first and second electrodes, an interlayer material-based electrode interlayer having a selectivity to etching greater than or equal to 2:1 relative to materials of the electrodes. During an etching of the stack, overetching is performed configured to laterally consume, in a horizontal direction, the interlayer material such that the electrode interlayer has a lateral recess greater than or equal to 10 nm.