Provided are a chalcogen compound having ovonic threshold switching characteristics, and a switching device, a semiconductor device, and/or a semiconductor apparatus which include the chalcogen compound. The chalcogen compound includes five or more elements and may have stable switching characteristics with a low off-current value (leakage current value). The chalcogen compound includes: selenium (Se) and tellurium (Te); a first element comprising at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); and a second element including germanium (Ge) and/or tin (Sn), and may further include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

An OxRAM oxide based resistive random access memory cell includes a first electrode; a layer M1Oss of a sub-stoichiometric oxide of a first metal; a layer M2N of a nitride of a second metal M2; a layer M3M4O of a ternary alloy of a third metal M3, a fourth metal M4 and oxygen O, or M3M4NO of a quaternary alloy of the third metal M3, the fourth metal M4, nitrogen N and oxygen O and a second electrode. The standard free enthalpy of formation of the ternary alloy M3M4O, noted ΔG.sub.f,T.sup.0 (M3M4O), or of the quaternary alloy M3M4NO, noted ΔG.sub.f,T.sup.0 (M3M4NO), is strictly less than the standard free enthalpy of formation of the sub-stoichiometric oxide M1Oss of the first metal M1, noted ΔG.sub.f,T.sup.0 (M1Oss), itself less than or equal to the standard free enthalpy of formation of any ternary oxynitride M2NO of the second metal M2, noted ΔG.sub.f,T.sup.0 (M2NO):
ΔG.sub.f,T.sup.0(M3M4O)<ΔG.sub.f,T.sup.0(M1Oss)≤ΔG.sub.f,T.sup.0(M2NO)
or ΔG.sub.f,T.sup.0(M3M4NO)<ΔG.sub.f,T.sup.0(M1Oss)≤ΔG.sub.f,T.sup.0(M2NO).

A resistance change device includes a first resistance change layer that occludes and discharges ions of at least one type, and resistance of the first resistance change layer, changes in accordance with an amount of the ions in such a manner that the resistance decreases when the ions are discharged and the resistance increases when the ions are occluded; a second resistance change layer that occludes and discharges the ions, and resistance of the second resistance change layer changes in accordance with the amount of the ions in such a manner that the resistance increases when the ions are discharged and the resistance decreases when the ions are occluded; and an ion conductive layer that carries the ions and is provided between the first resistance change layer and the second resistance change layer.

A method of forming a memory device includes forming a first electrode; forming a resistive switching layer over the first electrode; forming a dielectric layer over the resistive switching layer; forming a first opening in the dielectric layer, wherein the first opening passes through the dielectric layer and exposes the resistive switching layer; forming a first trench in the dielectric layer, wherein the first trench is directly above the first opening; and forming a second electrode having a step shape in the first opening and the first trench.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction.

A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.

The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.