Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm.sup.2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.

Provided is a memristor including an active electrode made of a first conductive material including an active metal; an inert electrode spaced from and facing toward the active electrode and made of a second conductive material having an ionization energy greater than the ionization energy of the first conductive material; and a resistive switching layer including: a porous insulating layer disposed between the active electrode and the inert electrode, wherein the porous insulating layer has through-channel holes defined therein extending from a bottom face to a top face thereof; and conductive filaments respectively formed inside the through-channel holes.

A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

A resistor-assembly includes a substrate, a heater, a resistor-element, and conductive-leads. The substrate is formed of a ceramic-material. The heater heats the resistor-assembly. The resistor-element is formed of an ion-conducting material that overlies the substrate. The conductive-leads are formed of a catalytic-metal that are in communication with a gas and in electrical contact with the resistor-element. The resistor-element is characterized by a resistance-value influenced by an oxygen-presence in the gas when the resistor-element is heated by the heater such that a resistor-temperature is greater than a temperature-threshold.

A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.

In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.