An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.

A semiconductor device according to an embodiment includes a substrate, a source electrode layer and a drain electrode layer that are disposed to be spaced apart from each other on the substrate, an active layer disposed on the substrate to contact the source electrode layer and the drain electrode layer, and a gate electrode layer disposed on the active layer. The active layer includes metal oxide capable of exsolving and reincorporating metal particles. The electrical resistance in the active layer is configured to be reversibly changed by exsolution and reincorporation of the metal particles.

Provided are a semiconductor device and a semiconductor apparatus. The semiconductor device may include a first electrode; a second electrode spaced apart from the first electrode; and a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer. In the semiconductor device, by doping the metal oxide, an off-current value (leakage current value) of the selection device layer may be reduced, and static switching characteristics may be implemented.

A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

A memory cell array of the present disclosure includes a plurality of memory cells 11 arranged in a first direction and a second direction different from the first direction. Each of the memory cells 11 includes a resistance-variable nonvolatile memory element and a selection transistor TR electrically connected to the nonvolatile memory element. The selection transistor TR is formed in an active region 80 provided in a semiconductor layer 60. At least a part of the active region 80 is in contact with an element isolation region 81 provided in the semiconductor layer 60. A surface of the element isolation region 81 is located at a position lower than a surface of the active region 80.

A preparation method of a silicon-based molecular beam heteroepitaxy material, a memristor, and use thereof are provided. A structure of the heteroepitaxy material is obtained by allowing a SrTiO.sub.3 layer, a La.sub.0.67Sr.sub.0.33MnO.sub.3 layer, and a (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 layer to successively grow on a P-type Si substrate. The silicon-based epitaxy structure is obtained by allowing a first layer of SrTiO.sub.3, a second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3, and a third layer of (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 (in which an atomic ratio of BaTiO.sub.3 to CeO.sub.2 is 0.5:0.5) to successively grow at a specific temperature and a specific oxygen pressure. The preparation method of a silicon-based molecular beam heteroepitaxy material adopts pulsed laser deposition (PLD), which is relatively simple and easy to control, and can achieve the memristor function and neuro-imitation characteristics. A thickness of the first buffer layer of SrTiO.sub.3 can reach 40 nm.

In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.

A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed over the substrate, a gate insulation layer disposed on the resistance change layer, a gate electrode layer disposed on the gate insulation layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed respectively over the substrate and disposed to contact a different portion of the resistance change layer.