To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.

An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M.sub.8XY.sub.6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M.sub.8XY.sub.6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.

A resistive random access memory includes a memory cell disposed at an intersection point between a first conductive line and a second conductive line. The memory cell includes a selector structure, a first current limiter structure and a resistor structure. The first current limiter structure is disposed between the selector structure and the first conductive line. The resistor structure is disposed between the selector structure and the second conductive line or between the first current limiter structure and the first conductive line.

An apparatus for high density memory with integrated logic. Specifically, a three terminal resistive random access memory (ReRAM) device having Schottky barriers that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes an insulating layer, a source region disposed on the insulating layer, a drain region disposed on the insulating layer, a binary or complex oxide memory material, a gate dielectric layer, and a gate electrode. As voltage is applied the Schottky barrier breaks down leading to the formation of a conductive anodic filament (CAF). The CAF is non-volatile and short-circuits the reverse-biased barrier thus keeping the device in a low resistance state. Removing the CAF switches the device back to a high resistance state. Thus, a new type of semiconductor device advantageously combines computation and memory further providing for very high density NAND chains.

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a multi-layer resistive random access memory (ReRAM) array is provided. Active layers of the array each comprise a plurality of ReRAM elements that each include a gate portion having a gate terminal and a memory cell portion with a source terminal and drain terminal. Insulating layers of the array alternate with the active layers and each comprise an insulating material between adjacent active layers. Wordlines span through more than one layer of the array, with each of the wordlines comprising a column of memory cell portions coupled via source terminals and drain terminals of column-associated ReRAM elements. Bitlines each span through an associated active layer of the array, with each of the bitlines comprising a row of gate portions coupled via at least gate terminals of row-associated ReRAM elements.

A memory device includes at least one memory cell which contains a resistive memory element having a conductive metal oxide located between a first electrode and a second electrode. The conductive metal oxide has a concentration of free electrons in thermodynamic equilibrium in a range from 1.0×10.sup.20/cm.sup.3 to 1.0×10.sup.21/cm.sup.3. A method of operating the memory device includes redistributing electron density to set and reset the device. An oxide barrier layer may be located between the conductive metal oxide and the second electrode.

A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.

The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a metal insulator metal (MIM) device including a metal ion-doped insulating layer and configured to perform integration and fire, and the MIM device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.

The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.