A device including a templating structure and a magnetic layer is described. The templating structure includes D and E. A ratio of D to E is represented by D.sub.1-xE.sub.x, with x being at least 0.4 and not more than 0.6. E includes a main constituent. The main constituent includes at least one of Al, Ga, and Ge. E includes at least fifty atomic percent of the main constituent. D includes at least one constituent that includes Ir. D includes at least 50 atomic percent of the at least one constituent. The magnetic layer is on the templating structure and includes at least one of a Heusler compound and an L1.sub.0 compound. The magnetic layer is in contact with the templating structure and being magnetic at room temperature.

A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.

The disclosure provides a magnetic random access memory element. The magnetic random access memory element includes a magnetic reference layer, a magnetic free layer, and a non-magnetic barrier layer between the magnetic free layer and the magnetic reference layer. The magnetic random access memory element further includes a MgO layer contacting the magnetic free layer. The MgO layer includes multiple homogeneous layers of MgO that provide excellent interfacial perpendicular magnetic anisotropy to the magnetic free layer while also having a low RA.

Provided is a precursor of a current-perpendicular-to-plane giant magnetoresistive element having a laminated structure of ferromagnetic metal layer/nonmagnetic metal layer/ferromagnetic metal layer, the precursor having a nonmagnetic intermediate layer containing a non-magnetic metal and an oxide in a predetermined ratio such that the distribution thereof is nearly uniform at the atomic level. Also provided is a current-perpendicular-to-plane giant magnetoresistive element having a current-confinement structure (CCP) which has: a current confinement structure region made of a conductive alloy and obtained by heat-treating a laminated structure of a ferromagnetic metal layer and a nonmagnetic intermediate layer at a predetermined temperature; and a high-resistance metal alloy region containing an oxide and surrounding the current confinement structure region.

A method for fabricating memory cell of magnetoresistive RAM includes forming a memory stack structure on a first electrode layer. The memory stack structure includes a SAF layer to serve as a pinned layer; a magnetic free layer and a barrier layer sandwiched between the SAF layer and the magnetic free layer. A second electrode layer is then formed on the memory stack structure. The SAF layer includes a first magnetic layer, a second magnetic layer, and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first and second magnetic layers, and the second metal element of the first magnetic layer and the second magnetic layer interfaces with the spacer layer.

A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.

In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

A spin orbit torque (SOT) memory device includes a MTJ device on a SOT electrode, where a first portion of the SOT electrode extends beyond a sidewall of the MTJ by a first length that is no greater than a height of the MTJ, and where a second portion of the first electrode extends from the sidewall and under the MTJ by a second length that is no greater than a width of the MTJ. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet.

A synapse device includes a perpendicularly magnetized ferrimagnetic racetrack layer, a tunneling barrier layer disposed on the racetrack layer and a reference layer including a perpendicular magnetic alloy. The racetrack layer, the tunneling layer and the reference layer have a channel portion and contact pad portions. First and second contacts are provided over the contact pad portions, and a third contact is provided over the channel portion, wherein the first and second contacts are electrically isolated from the third contact.

The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.