A method of manufacturing a substrate is disclosed. The method includes receiving a plurality of pixel elements, wherein each of the pixel elements includes data members; and transferring the data members to a plurality of exposing devices that are configured to conditionally expose the substrate with an incident energy beam when coupled with the data members, wherein different data members of one pixel element are transferred at different system cycles.

A linear stacked stage suitable for REBL may include a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis, the first upper fast stage configured to secure a first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first and second upper fast stages along a second axis.

Systems and method directed to digital pattern generator (DPG) having a mirror array in an e-beam lithography system are discussed. The mirror array includes a first bank of mirrors and a second bank of mirrors with a combination logic structure interposing the first and second banks of mirrors. An output data line extends from the first bank of mirrors to the combinational logic structure. An input data line that carries data associated with the second bank of mirrors is also provided to the combinational logic structure. An output data line extends from the combinational logic structure to second data bank.

The present disclosure provides a method for operating a dynamic pattern generator (DPG) having a mirror array. The method comprises receiving a clock signal, determining a time delay based on the period of the clock signal, determining a first clock signal for toggling a first group of mirror cells in the mirror array, determining a second clock signal, lagging behind the first clock signal by the time delay, for toggling a second group of mirror cells in the mirror array, toggling the first group of mirror cells in the mirror array in response to the first clock signal, and toggling the second group of the mirror cells in the mirror array in response to the second clock signal.

Disclosed is an apparatus in a semiconductor lithography system. The apparatus comprises a multiplexer and a plurality of imaging elements. The plurality is configured into a shift chain and an output of the shift chain is coupled to a data input of the multiplexer.

A method of fabricating a Digital pattern generator (DPG) device is disclosed. The method includes forming an etch-stop-layer (ESL) over a bonding pad in a first region over a substrate, forming a pixel well in the second region over the substrate, forming an anti-charging layer over the bonding pad and along sidewalls of the pixel well. The bonding pad is covered by the ESL during the forming of the anti-charging layer over the bonding pad. The method also includes removing the anti-charging layer over the bonding pad. Therefore, after removing the anti-charging layer over the bonding pad, the bonding pad remains covered by the ESL.

One embodiment relates to an apparatus for aberration correction in an electron beam lithography system. An inner electrode surrounds a pattern generating device, and there is at least one outer electrode around the inner electrode. Each of the inner and outer electrodes has a planar surface in a plane of the pattern generating device. Circuitry is configured to apply an inner voltage level to the inner electrode and at least one outer voltage level to the at least one outer electrode. The voltage levels may be set to correct a curvature of field in the electron beam lithography system. Another embodiment relates to an apparatus for aberration correction used in an electron based system, such as an electron beam inspection, or review, or metrology system. Other embodiments, aspects and features are also disclosed.

A dynamic pattern generator (DPG) device and method of making a DPG device are disclosed. The DPG device is used in semiconductor processing tools that require multiple electron-beams, such as direct-write lithography. The device is a self-aligned DPG device that enormously reduces the required tolerances for aligning the various electrode layers, as compared to other design configurations including the non-self-aligned approach and also greatly simplifies the process complexity and cost. A process sequence for both integrated and non-integrated versions of the self-aligned DPG device is described. Additionally, an advanced self-aligned DPG device that eliminates the need for a charge dissipating coating or layer to be used on the device is described. Finally, a fabrication process for the implementation of both integrated and non-integrated versions of the advanced self-aligned DPG device is described.