The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Provided is a method for manufacturing a semiconductor device suitable for achieving low wiring resistance between semiconductor elements that is bonded via an adhesive layer and multi-layered. The method according to the present invention is as follows. First, a wafer laminate (W) is prepared, the wafer laminate (W) including a wafer (10) having a circuit forming surface (10a), a wafer (20) having a main surface (20a) and a back surface (20b), and an adhesive layer (30) containing an SiOC-based polymer. Then, a hole (H) is formed in the wafer laminate (W) by etching the wafer laminate (W) from the wafer (20) side via a mask pattern masking a portion of the main surface (20a) side of the wafer (20), the hole (H) extending through the wafer (20) and the adhesive layer (30) and reaching a wiring pattern (12b) in the wafer (10). Then, an insulating film (41) is formed on an inner surface of the hole (H). Then, the insulating film (41) on a bottom surface of the hole (H) is removed. Then, the wafer laminate (W) is subjected to a cleaning treatment (an oxygen plasma treatment and/or an Ar sputtering treatment). Then, a conductive portion is formed in the hole (H).

A substrate processing method performed in a chamber of a substrate processing apparatus is provided. The chamber includes a substrate support, an upper electrode, and a gas supply port. The substrate processing method includes (a) providing the substrate on the substrate support; (b) supplying a first processing gas into the chamber; (c) continuously supplying an RF signal into the chamber while continuously supplying a negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber; and (d) supplying a pulsed RF signal while continuously supplying the negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber. The process further includes repeating alternately repeating the steps (c) and (d), and a time for performing the step (c) once is 30 second or shorter.

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

A semiconductor structure is provided. The semiconductor structure includes an epitaxial structure over a semiconductor substrate. The semiconductor structure also includes a conductive feature over the semiconductor substrate. The conductive feature includes a high-k dielectric layer and a metal layer on the high-k dielectric layer, and a top surface of the metal layer is below a top surface of the high-k dielectric layer. The semiconductor structure further includes a metal-semiconductor compound layer formed on the epitaxial structure. In addition, the semiconductor structure includes a first metal contact structure formed on the top surface of the metal layer of the conductive feature. The semiconductor structure further includes a second metal contact structure formed on the metal-semiconductor compound layer.

A substrate processing method includes: preparing a substrate which includes a base having an epitaxial layer formed by epitaxial growth, and an insulating film formed on the base and having a penetration portion that exposes the epitaxial layer; forming a silicon film on a surface of the epitaxial layer exposed from the penetration portion rather than a side wall of the penetration portion; and forming a metal film on the silicon film formed on the surface of the epitaxial layer rather than the side wall of the penetration portion, and causing the silicon film to react with the metal film to form a metal silicide film.

A method of gap filling a feature on a substrate decreases the feature-to-feature gap fill height variation by using a tungsten halide soak treatment. In some embodiments, the method may include heating a substrate to a temperature of approximately 350 degrees Celsius to approximately 450 degrees Celsius, exposing the substrate to a tungsten halide gas at a process pressure of approximately 5 Torr to approximately 25 Torr, soaking the substrate for a soak time of approximately 5 seconds to approximately 60 seconds with the tungsten halide gas, and performing a metal preclean process and a gap fill deposition on a plurality of features on the substrate after soaking of the substrate has completed.

A fin field effect transistor device structure includes a fin structure formed over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure formed over the fin structure. The fin field effect transistor device structure also includes a contact structure with a concave top surface formed over the source/drain epitaxial structure. The fin field effect transistor device structure also includes a barrier layer conformally wrapped around the contact structure. The fin field effect transistor device structure also includes a via structure formed over the contact structure. The concave top surface of the contact structure is below the top surface of the barrier layer.

An aqueous composition includes (A) from 0.001 to 20 mass % of one or more kinds of fluorine-containing compounds selected from tetrafluoroboric acid, hexafluorosilicic acid, hexafluoroaluminic acid, hexafluorotitanic acid and a salt thereof, with respect to the total amount of the aqueous composition; and (B) from 0.0001 to 10 mass % of one or more kinds of compounds selected from a C.sub.4-13 alkylphosphonic acid, a C.sub.4-13 alkylphosphonate ester, a C.sub.4-13 alkyl phosphate and a salt thereof, with respect to the total amount of the aqueous composition.

A semiconductor device includes a first dielectric layer over a device base layer, the first dielectric layer having a first opening with a first sidewall; a first interconnect segment extending through the first opening; and a cap layer over a top surface of the first interconnect segment, wherein the cap layer comprises a first metal, carbon, and nitrogen.