In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.

An aqueous composition includes (A) from 0.0001 to 10 mass % of one or more kinds of compounds selected from a C.sub.4-13 alkylphosphonic acid, a C.sub.4-13 alkylphosphonate ester, a C.sub.4-13 alkyl phosphate and a salt thereof, with respect to the total amount of the aqueous composition; and (B) from 0.0001 to 50 mass % of an acid other than the C.sub.4-13 alkylphosphonic acid, the C.sub.4-13 alkylphosphonate ester and the C.sub.4-13 alkyl phosphate or a salt thereof, with respect to the total amount of the aqueous composition.

A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.

A substrate processing method includes preparing a substrate including an etching target film and a mask; etching the etching target film through the mask by plasma; and heat-treating the substrate at a preset temperature after the etching of the etching target film.

A method for manufacturing a memory includes: providing a substrate having a core region provided with a word line; forming a dielectric layer on the substrate, and etching the dielectric layer to form a first filling hole exposing the word line; forming a barrier layer on a hole wall of the first filling hole, where the barrier layer located in the first filling hole surrounds and forms a first intermediate hole exposing the word line; etching the word line exposed in the first intermediate hole to remove a first residue on the word line; and forming in the first intermediate hole a first wire electrically connected to the word line.

Examples of the present invention include a method for removing halogen-containing residues from a substrate. The method includes transferring a substrate to a substrate processing system through a first chamber volume of a load lock chamber. The load lock chamber is coupled to a transfer chamber of the substrate processing system. The substrate is etched in one or more processing chambers coupled to the transfer chamber of the substrate processing system with chemistry from a showerhead disposed over a heated substrate support assembly. The chemistry includes halogen. Halogen-containing residues are removed from the etched substrate in a second chamber volume of the load lock chamber. Cooling the etched substrate in a cooled substrate support assembly of the load lock chamber after removing the halogen-containing residue.

A treatment liquid contains water, hydroxylamine, and one or more kinds of hydrazines selected from the group consisting of hydrazine, a hydrazine salt, and a hydrazine derivative, in which a total content of the hydrazines is 1 part by mass or less with respect to 100 parts by mass of the hydroxylamine.

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CH.sub.xF.sub.y gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH.sub.3—NF.sub.3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.