A polishing apparatus is provided. The polishing apparatus includes: a polishing unit configured to polish a substrate by bringing a polishing tool into contact with the substrate and moving the substrate relatively to the polishing tool; a cleaning unit; and a first transfer robot configured to transfer the substrate before polishing to the polishing unit and/or configured to transfer the substrate after polishing from the polishing unit to the cleaning unit. The cleaning unit includes: at least one cleaning module, a buff processing module configured to perform a buff process to the substrate, and a second transfer robot configured to transfer the substrate between the cleaning module and the buff processing module, the second transfer robot being different from the first robot.

A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

A cleaning brush for a semiconductor fabrication process is provided. The cleaning brush includes a core and a brush member. The core includes a circumferential portion and a closed end portion. The circumferential portion surrounds a rotation axis of the cleaning brush and defines an inlet opening for receiving a fluid. The closed end portion is connected to an end of the circumferential portion that is opposite to the inlet opening along the rotation axis. At least one elongated conduit is defined within the core and fluidly communicated with the inlet opening, and the circumferential portion includes a plurality of outlet channels passing therethrough to fluidly communicate with the elongated conduit, the outlet channels being tilted outwardly toward the closed end portion. The brush member is connected to an outer surface of the circumferential portion and covers all of the outlet channels.

Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

A system for performing a Chemical Mechanical Polishing (CMP) process is provided. The system includes a CMP module configured to polish a semiconductor wafer. The system further includes a cleaning brush assembly configured to clean the semiconductor wafer. The cleaning brush includes a rotation shaft and a brush member surrounding a segment of the rotation shaft. The system also includes an agitation transducer arranged to be distant from the brush member and configured to produce an agitated cleaning liquid to clean the cleaning brush assembly.

A substrate processing method and a substrate processing apparatus are provided, which solve problems of pattern collapse and particles. The substrate processing method includes: a surface modification step of modifying a surface of a substrate having an oxide thereon to improve or reduce roughness of the surface; a surface cleaning step of supplying a treatment liquid to the modified surface of the substrate to clean the surface of the substrate with the treatment liquid; and a hydrophobization step of supplying a hydrophobizing agent to the cleaned surface of the substrate to hydrophobize the surface of the substrate.

The present invention relates to a cleaning liquid on a silicon oxide film and/or a silicon nitride film, and the cleaning liquid contains (i) at least one compound selected from the group consisting of a compound represented by the formula (1), a compound represented by formula (2), a compound represented by formula (3), and a compound represented by the formula (4); and (ii) a reducing agent;

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in the above formulas, R.sub.1 to R.sub.12 and n are the same as the definitions described in the description.

The present invention provides a means by which it is possible to sufficiently suppress an organic residue while favorably decreasing a ceria residue on a polished object to be polished obtained after being polished using a polishing composition containing ceria. The present invention relates to a composition for surface treatment, which is for a surface treatment of a polished object to be polished obtained after being polished using a polishing composition containing ceria, contains a carboxy group-containing (co)polymer having a structural unit derived from a monomer having a carboxy group or a salt group of the carboxy group, a SO.sub.x or NO.sub.y partial structure-containing compound having a partial structure represented by SO.sub.x or NO.sub.y (where x and y each independently denote a real number 1 to 5), and a dispersing medium, and has a pH of 1 or more and 8 or less.

A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.