A substrate processing apparatus includes a processing chamber; a susceptor provided in the processing chamber, wherein the susceptor is configured to support a substrate; a first plasma generator disposed on one side of the processing chamber; and a second plasma generator disposed on another side of the processing chamber, wherein the second plasma generator is configured to generate plasma by simultaneously supplying a sinusoidal wave signal and a non-sinusoidal wave signal to the susceptor. By using a substrate processing apparatus, a signal source device, and a method of processing a material layer according to the inventive concept, a smooth etched surface may be obtained for a crystalline material layer without a risk of device damage by RDC.

Methods for processing a workpiece are provided. Conducting a thermal treatment on a workpiece are provided. The workpiece contains at least one layer of metal. The method can include generating one or more species from a process gas. The process gas can include hydrogen or deuterium. The method can include filtering the one or more species to create a filtered mixture and exposing the workpiece to the filtered mixture. An oxidation process on a workpiece are provided. The method can be conducted at a process temperature of less than 350° C.

A cleaning liquid for cleaning a substrate in which at least one of molybdenum and tungsten is exposed on a surface, in which the cleaning liquid includes at least one of a compound represented by General Formula (a1), a hydrate of the compound, and a salt of the compound, a water-soluble basic compound with a pH of 9.5 or more in a 0.1 M aqueous solution, which is measured at 23° C. with a pH meter, and water. In General Formula (a1), R.sup.1 and R.sup.2 each independently represents an organic group including no carbonyl group or a hydrogen atom

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A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Methods for cleaning integrated circuit (IC) wafers after undergoing planarization processes (for example, chemical mechanical polishing processes) and associated cleaning units and/or planarization units are disclosed herein. An exemplary method includes configuring outlet areas of spray nozzles to deliver a cleaning solution to optimal locations of the IC wafer and delivering the cleaning solution via the spray nozzles having the configured outlet areas to the IC wafer. Each of the outlet areas is configured to achieve a particular velocity of the cleaning solution exiting the outlet area, such that the cleaning solution reaches a particular location of the IC wafer depending on the particular velocity. In some implementations, the cleaning solution enters inlet areas of the spray nozzles at the same flow rate and the cleaning solution exits the outlet areas of the spray nozzles at different velocities.

A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder. The gate structure includes at least two ceramic or metal layers, and the gate dielectric material is made of a high-k dielectric material. A substrate having the gate structure and gate dielectric material formed thereon is disposed in the processing region, and the temperature of the substrate is maintained at about 60 degrees Celsius or higher. By etching the gate structure using fluorine radicals at a temperature greater or equal to 60 degrees Celsius, the at least two ceramic or metal layers have a flat cross sectional profile.

Techniques relate to treating metallic interconnects of semiconductors. A metallic interconnect is formed in a layer. A metallic cap is disposed on top of the metallic interconnect. Any metallic residue, formed during the disposing of the metallic cap, is converted into insulating material.

A method and apparatus for removing volatile residues from a substrate are provided. In one embodiment, a method for volatile residues from a substrate includes providing a processing system having a load lock chamber and at least one processing chamber coupled to a transfer chamber, treating a substrate in the processing chamber with a chemistry comprising halogen, and removing volatile residues from the treated substrate in the load lock chamber.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

A method of manufacturing a semiconductor device is provided. The method includes depositing a first interconnect metal layer on a substrate; depositing a first barrier metal layer on the first interconnect metal layer; depositing a first dielectric layer on the first barrier metal layer; depositing a second barrier metal layer on the first dielectric layer; etching the second barrier metal layer to form a MIM capacitor region and a thin film resistor region; forming a hard mask on the second barrier metal layer and the first dielectric layer; forming an isolated interconnect pattern between the MIM capacitor region and the thin film resistor region; depositing an inter-metal dielectric layer on the hard mask; forming Via holes in the MIM capacitor region and the thin film resistor region, and filling the Via holes with metal to form a Via contact layer.