H01L21/02071

Plasma processing method

The present invention provides a plasma processing method for subjecting a sample on which a metal element-containing film is disposed to plasma etching in a processing chamber. The method comprises: subjecting an inside of the processing chamber to plasma cleaning using a boron element-containing gas; removing the boron element using plasma after the plasma cleaning; subjecting the inside of the processing chamber to plasma cleaning using a fluorine element-containing gas after removing the boron element; depositing a deposited film in the processing chamber by plasma using a silicon element-containing gas after the plasma cleaning using the fluorine element-containing gas; and subjecting the sample to plasma etching after depositing the deposited film.

Chemical solution, method for manufacturing chemical solution, and method for treating substrate

The present invention provides a chemical solution, which demonstrates excellent etching performance for transition metal-containing substances and has excellent defect inhibition performance, a method for manufacturing the chemical solution, and a method for treating a substrate. The chemical solution according to an embodiment of the present invention includes one or more kinds of periodic acids selected from the group consisting of a periodic acid and a salt thereof, one or more kinds of first metal components selected from the group consisting of Ti and Zr, and water. In a case where the chemical solution includes one kind of first metal component, a content of the one kind of first metal component is 1 ppt by mass to 100 ppm by mass with respect to a total mass of the periodic acids. In a case where the chemical solution includes two kinds of first metal components, a content of both the two kinds of first metal components is equal to or smaller than 100 ppm by mass with respect to the total mass of the periodic acids, and a content of at least one of the two kinds of first metal components is equal to or greater than 1 ppt by mass with respect to the total mass of the periodic acids.

CLEANING FORMULATION FOR REMOVING RESIDUES ON SURFACES

This disclosure relates to a cleaning composition that contains 1) at least one redox agent; 2) at least one first chelating agent, the first chelating agent being a polyaminopolycarboxylic acid; 3) at least one metal corrosion inhibitor, the metal corrosion inhibitor being a substituted or unsubstituted benzotriazole; 4) at least one pH adjusting agent, the pH adjusting agent being a base free of a metal ion; and 5) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.

Composition for removing ruthenium

The present invention addresses the problem of providing a remover composition which can sufficiently remove ruthenium (Ru) remaining on substrates and can be inhibited from evolving RuO.sub.4 gas. The remover composition, which is for removing ruthenium remaining on substrates, has a pH at 25° C. of 8 or higher and includes one or more pH buffer ingredients.

Tuning Threshold Voltage Through Meta Stable Plasma Treatment
20220139712 · 2022-05-05 ·

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
20220139923 · 2022-05-05 ·

The present application relates to the technical field of manufacturing semiconductor, and in particular to a method of manufacturing semiconductor structure and a semiconductor structure. The method of manufacturing semiconductor structure includes: forming a conductive layer on a substrate, and removing part of the conductive layer to form a contact structure composed of a plurality of contact pads; where each of the contact pads is electrically connected to a transistor structure on the substrate; and, after the contact pads are formed, removing residual core on top ends of the contact pads away from the substrate by dry etching.

Semiconductor Device and Method for Manufacture

A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

SEMICONDUCTOR DEVICE FABRICATION WITH REMOVAL OF ACCUMULATION OF MATERIAL FROM SIDEWALL
20220122850 · 2022-04-21 ·

A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

Abatement and strip process chamber in a dual loadlock configuration

Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume.

Semiconductor device with an interconnect structure and method for forming the same

A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.