Stripping solutions that may replace an etching resist ashing process are provided. The stripping solutions are useful for fabricating circuits and/or forming electrodes and/or packaging/bumping applications on semiconductor devices for semiconductor integrated circuits with good photoresist removal efficiency and with low silicon oxide etch rate and low metal etch rates. Methods for their use are similarly provided. The preferred stripping agents contain polar aprotic solvent, water, hydroxylamine, corrosion inhibitor, quaternary ammonium hydroxide and optional surfactant. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.

The present invention addresses the problem of providing a remover composition which can sufficiently remove ruthenium (Ru) remaining on substrates and can be inhibited from evolving RuO.sub.4 gas. The remover composition, which is for removing ruthenium remaining on substrates, has a pH at 25° C. of 8 or higher and includes one or more pH buffer ingredients.

The present invention provides a chemical liquid that causes a small variation in a dissolving amount of a first metal-containing substance in a case where the chemical liquid is applied to an object to be treated containing the first metal-containing substance. The present invention also provides a method for treating an object to be treated. The chemical liquid according to an embodiment of the present invention contains water, a hydroxylamine compound selected from the group consisting of hydroxylamine and a hydroxylamine salt, and a specific compound represented by Formula (1).

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A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume.

The present invention provides an array substrate and a method for manufacturing the array substrate. The method includes: providing a substrate and forming a buffer layer, a poly-silicon layer and a first gate insulating layer sequentially on the substrate; and forming a first gate metal layer on the first gate insulating layer, forming a first photoresist stickiness maintaining metal film on the first gate metal layer, forming a patterned gate electrode and a first patterned photoresist stickiness maintaining metal on a surface of the patterned gate electrode by a first developing process.

A substrate (1) having a GaN surface (2) is immersed in a catalyst metal solution (4) containing potassium hydroxide and a plating catalyst metal salt while being irradiated with ultraviolet light to deposit a catalyst metal (5) on the GaN surface (2). A metal film (7) is formed on the GaN surface (2) having the catalyst metal (5) deposited thereon by electroless plating.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

A method of cleaning a surface of a substrate uses alcohol and water treatments. The method may include applying an alcohol treatment on a surface of the substrate with the alcohol treatment configured to provide surface reduction and applying a water treatment to the surface of the substrate with the water treatment configured to enhance selectivity of at least a portion of the surface for a subsequent barrier layer process by removing alcohol from the at least a portion of the surface. The water treatment may be performed simultaneously with the alcohol treatment or performed after the alcohol treatment. The water treatment may include vaporized water or water injected into a plasma to produce hydrogen or oxygen radicals.

This disclosure relates to a cleaning composition that contains 1) hydroxylamine; 2) a chelating agent; 3) an alkylene glycol; 4) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.