A substrate processing method includes holding a substrate; and supplying an etching liquid to the substrate held in the holding of the substrate. The etching liquid contains an etching agent configured to etch a metal-based first material and a silicon-based second material exposed on the substrate and a protection agent configured to react with the second material between the first material and the second material to form a protection layer on a surface of the second material. Here, the etching agent is a liquid which contains fluorine atoms and an organic solvent and substantially does not contain water, and the protection layer protects the second material from etching with the etching agent.

The present invention discloses a stacked semiconductor chip structure and its process wherein the stacked semiconductor chip structure comprises a substrate as well as P-type semiconductor layers and N-type semiconductor layers which are stacked one by one on the substrate, wherein the P-type semiconductor layers and the N-type semiconductor layers are arranged alternately, there are at least two P-type semiconductor layers and at least two N-type semiconductor layers. The present invention uses the chemical vapor deposition method to stack and form the P-type semiconductor layers and the N-type semiconductor layers, uses the physical etching and the plasma cleaning to form the conducting layers and thus avoids using the photo masks, the photo resist and the mask aligners for the manufacture of semiconductor chips, reduces the complexity of semiconductor chip processes and increases the yield of semiconductor chip products.

A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

A cleaning composition and process for cleaning an in-process microelectronic device substrate, e.g., by post-chemical mechanical polishing (CMP) cleaning, to remove residue from a surface thereof, wherein the cleaning composition may be especially effective for cleaning a substrate surface that includes exposed metal such as cobalt, copper, or both, along with dielectric or low k dielectric material, and wherein the cleaning composition includes corrosion inhibitor to inhibit corrosion of the exposed metal.

A method for preventing the collapse of patterned, high aspect ratio features formed in semiconductor substrates upon removal of an initial fluid of the type used to clean etch residues from the spaces between the features. In the present method, the spaces are at least partially filled with a displacement solution, such as via spin coating, to substantially displace the initial fluid. The displacement solution includes at least one solvent and at least one fill material in the form of a water-soluble polymer such as polyvinylpyrrolidone (PVP) or polyacrylamide (PAAM). The solvent is then volatized to deposit the fill material in substantially solid form within the spaces. The fill material may be removed by known plasma ash process via a high ash rate as compared to use of current fill materials, which prevents or mitigates silicon loss.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

Provided are a substrate treatment method and a substrate treatment equipment enabling greater suppression of corrosion or oxidation of metal wiring exposed on a substrate surface. The present invention relates to a substrate treatment equipment having a treatment chamber wherein a substrate is disposed, and whereto a substrate treatment solution for treating the substrate is supplied. This equipment is provided with an inert gas filling mechanism for filling with an inert gas the interior of the treatment chamber wherein the substrate is disposed, and, near or inside the treatment chamber, a catalytic unit filled with a platinum-group metal catalyst wherethrough a hydrogen-dissolved water including hydrogen added to ultra-pure water is passed. Obtained by passing the hydrogen-dissolved water through the platinum-group metal catalyst, a hydrogen-dissolved treatment solution is supplied as the substrate treatment solution into the treatment chamber by the equipment.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.