H01L21/02074

METHODS FOR FORMING ELECTRONIC APPARATUS WITH TIERED STACKS HAVING CONDUCTIVE STRUCTURES ISOLATED BY TRENCHES, AND RELATED ELECTRONIC APPARATUS AND SYSTEMS
20210358890 · 2021-11-18 ·

Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

Semiconductor Device and Method
20210351039 · 2021-11-11 ·

An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Composition for surface treatment, method for producing composition for surface treatment, surface treatment method, and method for producing semiconductor substrate

A composition for surface treatment according to the present invention is used for treating the surface of an object to be polished after polishing, the composition for surface treatment including: a water-soluble polymer having a constituent unit derived from glycerin; an acid; and water, wherein the composition for surface treatment has a pH of 5 or lower.

CLEANING METHOD WITH IN-LINE SPM PROCESSING

A method for removing particulates from a plurality of substrates includes opening a first access port in a top of a first container holding a cleaning fluid bath, inserting a first substrate through the first access port to a first support, closing the first access port, opening a second access port in the top of the first container, inserting a second substrate through the second access port to a second support, closing the second access port, opening the first access port, removing the first substrate through the first access port and delivering the first substrate into a rinsing station, closing the first access port, opening the second access port, removing the second substrate through the second access port and delivering the second substrate into the rinsing station, and closing the second access port.

STEAM-ASSISTED SINGLE SUBSTRATE CLEANING PROCESS AND APPARATUS

The present disclosure relates to a method and apparatus for cleaning a substrate. The method includes rotating a substrate disposed on a substrate support and spraying a front side of the substrate using steam through a front side nozzle assembly. A back side of the substrate is sprayed using steam through a back side dispenser assembly. A heated chemical is dispensed over the front side of the substrate.

SURFACE TREATMENT COMPOSITION, SURFACE TREATMENT METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE
20230313069 · 2023-10-05 · ·

A means capable of sufficiently removing residues remaining on the surface of a polished object is to be provided. The present invention relates to a surface treatment composition, containing components (A) to (C), and having pH of more than 7.0:

the component (A): a quaternary nitrogen-containing onium salt compound having at least one of a linear or branched alkyl group having 7 or more carbon atoms and a linear or branched alkenyl group having 7 or more carbon atoms,

the component (B): a nonionic polymer,

the component (C): a buffer represented by a formula:


A-COO—NH.sub.4.sup.+.

Semiconductor device cleaning solution, method of use, and method of manufacture

A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.

TREATMENT LIQUID AND SUBSTRATE TREATMENT METHOD

An object of the present invention to provide a treatment liquid for a semiconductor device, where the treatment liquid has an excellent corrosion prevention property with respect to a metal-containing layer and excellent removability of an object to be removed, and also has excellent solubility in a post-treatment liquid. In addition, an object of the present invention is to provide a substrate treatment method using the treatment liquid.

The treatment liquid of the present invention is a treatment liquid for a semiconductor device, which contains water, a removing agent, and a copolymer, and the copolymer has a first repeating unit having at least one group selected from the group consisting of a primary amino group, a secondary amino group, a tertiary amino group, and a quaternary ammonium cation, and a second repeating unit different from the first repeating unit.

Method of selective deposition for forming fully self-aligned vias
11658068 · 2023-05-23 · ·

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO.sub.2 film on the metal-containing catalyst layer on the dielectric material.

SURFACE TREATMENT COMPOSITION, METHOD FOR PRODUCING SURFACE TREATMENT COMPOSITION, SURFACE TREATMENT METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE

To provide a means capable of sufficiently removing organic residues present on the surface of a polishing object after polishing containing silicon oxide or polysilicon.

A surface treatment composition contains a polymer having a constituent unit represented by Formula (1) below and water and is used for treating the surface of a polishing object after polishing,

##STR00001## in which, in Formula (1) above, R.sup.1 is a hydrocarbon group having 1 to 5 carbon atoms and R.sup.2 is a hydrogen atom or a hydrocarbon group having 1 to 3 carbon atoms.