The present disclosure generally relates to substrate processing methods, such as etching methods with noble gases at low temperatures. In an aspect, the method includes exposing a substrate, a first layer comprising a gas, and a fluorine-containing layer to energy to form a passivation layer while maintaining the substrate at conditions encompassing a triple point temperature of the gas, the substrate positioned in a processing region of a processing chamber. The method further includes etching the substrate with ions.

Exemplary methods of semiconductor processing may include providing a boron-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the boron-containing precursor and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a boron-and-carbon-containing layer on the substrate.

The glass for covering a semiconductor element contains: in mol %, as a glass composition, SiO.sub.2: 20% to 36%, ZnO: 8% to 40%, B.sub.2O.sub.3: 10% to 24%, Al.sub.2O.sub.3: 10% to 20%, and MgO+CaO: 8% to 22%, in which SiO.sub.2/ZnO is 0.6 or more and less than 3.3 in terms of a molar ratio, and a lead component is substantially not contained.

A method for forming a film that includes forming a boron nitride film on a substrate, and forming a boron-containing silicon film on the boron nitride film.

Methods and systems for depositing a boron nitride film on a substrate are disclosed. More particularly, the disclosure relates to methods and systems that can be used for depositing a boron nitride film by a pulsed CVD process.

A hardmask-forming compound, a hardmask composition, and a method of manufacturing an integrated circuit (IC), the hardmask-forming compound including a moiety represented by Formula 1:

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Disclosed are a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), a method for fabricating the same, an array substrate, a display panel, and a display device. The LTPS TFT includes an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate. The gate insulating layer is arranged between the active layer and the gate, and a graphene oxide layer which is arranged between the active layer and the gate insulating layer. Since the graphene oxide layer is arranged between the active layer and the gate insulating layer, the interface between the active layer and the gate insulating layer of polycrystalline (P-Si) has a reduced roughness and interfacial defect density, and a pre-cleaning process is not necessary for the gate insulating layer.

A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion.

Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.

The present disclosure relates to the technical field of semiconductors, and provides a method of processing a photoresist layer, and a photoresist layer. The method of processing a photoresist layer includes: forming a photoresist layer on a target layer, where the photoresist layer includes a first part close to the target layer and a second part away from the target layer; performing first exposure processing on the photoresist layer, and forming an exposure image in the first part of the photoresist layer; processing the second part of the photoresist layer by using a first process, such that the second part forms a third part, where a photosensitivity of the third part is higher than that of the first part; and stripping the third part.