LOW-TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR, AND MANUFACTURING METHOD FOR FABRICATING THE SAME, ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

Abstract

Disclosed are a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), a method for fabricating the same, an array substrate, a display panel, and a display device. The LTPS TFT includes an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate. The gate insulating layer is arranged between the active layer and the gate, and a graphene oxide layer which is arranged between the active layer and the gate insulating layer. Since the graphene oxide layer is arranged between the active layer and the gate insulating layer, the interface between the active layer and the gate insulating layer of polycrystalline (P-Si) has a reduced roughness and interfacial defect density, and a pre-cleaning process is not necessary for the gate insulating layer.

Claims

1. An LTPS TFT comprising an active layer, a source, a drain, a gate, and a gate insulating layer on a substrate, wherein the gate insulating layer is arranged between the active layer and the gate and wherein the LTPS TFT further comprises a graphene oxide layer which is arranged between the active layer and the gate insulating layer.

2. The LTPS TFT of claim 1, wherein the active layer is arranged on the substrate, the graphene oxide layer is arranged on the active layer, and the gate insulating layer covers a stack of the active layer and the graphene oxide layer.

3. The LTPS TFT of claim 1, wherein the gate is arranged on the substrate, the gate insulating layer covers the gate, the graphene oxide layer is arranged on the gate insulating layer, and the active layer is arranged on the graphene oxide layer.

4. The LTPS TFT of claim 1, wherein the graphene oxide layer has a thickness about 10-20 nm.

5. The LTPS TFT of claim 1, wherein the LTPS TFT further comprises a buffer layer which is formed on the substrate.

6. The LTPS TFT of claim 5, wherein the buffer layer is made from silicon oxide, silicon nitride, or silicon oxynitride.

7. The LTPS TFT of claim 5, wherein the buffer layer is made from silicon oxide and has a thickness about 50-100 nm.

8. The LTPS TFT of claim 5, wherein the buffer layer is made from silicon nitride and has a thickness about 100-300 nm.

9. The LTPS TFT of claim 2, further comprising an interlayer dielectric layer which covers the gate, wherein the source and the drain are connected to the active layer through vias which run through the graphene oxide layer, the gate insulating layer and the interlayer dielectric layer, respectively.

10. The LTPS TFT of claim 3, further comprising an interlayer dielectric layer which covers a stack of the active layer and the graphene oxide layer, wherein the source and the drain are connected to the active layer through vias which run through the interlayer dielectric layer, respectively.

11. The LTPS TFT of claim 1, wherein the active layer comprises a source contact area and a drain contact area which are doped; the source is arranged on the source contact area and connected to the source contact area; and the drain is arranged on the drain contact area and connected to the drain contact area.

12. An array substrate, comprising the LTPS TFT of claim 1, a planarization layer covering the LTPS TFT, and a pixel electrode, wherein the pixel electrode is connected to the drain of the LTPS TFT through a via which runs through the planarization layer.

13. A display panel, comprising the array substrate of claim 12.

14. A display device, comprising the display panel of claim 13.

15. A method for fabricating an LTPS TFT comprising: forming on a substrate an active layer, a source, a drain, a gate, and a gate insulating layer wherein the gate insulating layer is arranged between the active layer and the gate, wherein the method further comprises forming a graphene oxide layer between the active layer and the gate insulating layer.

16. The method of claim 15, wherein the step of forming the graphene oxide layer comprises: preparing a graphene oxide dispersion; spin coating the graphene oxide dispersion on the active layer or the gate insulating layer; and baking the graphene oxide dispersion to form the graphene oxide layer.

17. The method of claim 16, wherein the step of preparing the graphene oxide dispersion comprises: preparing graphene oxide by oxidizing graphite with an oxidizing agent; and disperse the graphene oxide in a solvent to prepare the graphene oxide dispersion.

18. The method of claim 17, wherein the oxidizing agent comprises concentrated sulfuric acid and potassium permanganate.

19. The method of claim 17, wherein the solvent is an ethanol aqueous solution with a volume percentage of 10%.

20. The method of claim 16, further comprising: after baking the graphene oxide dispersion to form the graphene oxide layer, performing chemical mechanical polishing on the graphene oxide layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to explain the technical solutions in embodiments of the present disclosure more clearly, the drawings to be used in the description of the embodiments will be introduced briefly in the following. Apparently, the drawings described below are only some embodiments of the present disclosure.

[0039] FIG. 1 is a structural diagram for illustrating an LTPS TFT in an embodiment of the present disclosure;

[0040] FIG. 2 is a structural diagram for illustrating an LTPS TFT in an embodiment of the present disclosure;

[0041] FIG. 3 is a structural diagram for illustrating an LTPS TFT in an embodiment of the present disclosure;

[0042] FIG. 4 is a structural diagram for illustrating an array substrate in an embodiment of the present disclosure;

[0043] FIG. 5 is a structural diagram for illustrating an array substrate in an embodiment of the present disclosure;

[0044] FIG. 6 is a flow chart for illustrating a method for fabricating an LTPS TFT in an embodiment of the present disclosure; and

[0045] FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, 7I, 7J, 7K, 7L, 7M, 7N are structural diagrams for illustrating processing stages of an LTPS TFT in an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

[0046] Specific embodiments of the present disclosure will be further described hereinafter with reference to the drawings and embodiments. The following embodiments are only used for explaining more clearly the technical solution of the present disclosure rather than limiting the protection scope of the present disclosure.

[0047] Reference numerals: 100, 200 substrate; 102, 202 buffer layer; 104, 210 active layer; 104S source contact area; 104D drain contact area; 106, 208 graphene oxide layer; 108, 206 gate insulating layer; 110, 204 gate; 112, 212 interlayer dielectric layer; 114 via; 116 source/drain electrode layer; 118, 214 source electrode; 120, 216 drain electrode; 122, 218 planarization layer; 124, 220 pixel electrode; and 151, 152, 153, 154 photoresist layer.

[0048] According to a first aspect of the present disclosure, it is provided an LTPS TFT. As shown in FIG. 1, the LTPS TFT comprises an active layer 104, a source 118, a drain 120, a gate 110, and a gate insulating layer 108 between the active layer 104 and the gate 110, which are arranged on a substrate 100. According to the present disclosure, the LTPS TFT further comprises a graphene oxide layer 106 which is arranged between the active layer 104 and the gate insulating layer 108.

[0049] In the LTPS TFT of the present disclosure, the graphene oxide layer is arranged between the P-Si active layer and the gate insulating layer, so as to solve the problem about the roughness and interfacial defect density of the interface between the P-Si active layer and the gate insulating layer. In graphene oxide, a planar layer structure is formed in which sp2 hybrid orbitals of carbon atoms are combined to in hexagonal and honeycomb lattices. Graphene oxide has a relatively high ion mobility and has a conjugated it-bond electron cloud distribution. As compared with P-Si, graphene oxide has a smaller molecular structure, so that the roughness and interfacial defect density of the interface between the P-Si active layer and the gate insulating layer are further reduced, so as to increase the characteristics of LTPS TFT. Due to the application of a graphene oxide layer, the gate insulating layer pre-cleaning process is not required during the process for fabricating the LTPS TFT, and this simplifies the fabricating process and reduces cost.

[0050] As an example, the graphene oxide layer has a thickness about 10-20 nm to provide an even surface. For example, the graphene oxide layer has a thickness of 10 nm.

[0051] As an example, the LTPS TFT further comprises a buffer layer 102 which is formed on the substrate 100, as shown in FIG. 2. By arranging the buffer layer 102 on the substrate 100, the adhesion strength between the TFT to be formed and the substrate 100 is increased. In the embodiment shown in FIG. 2, the buffer layer 102 isolates the substrate 100 from the active layer 104 of TFT, and prevents impurities the substrate 100 from entering the active layer 104 which otherwise would affect the performance of TFT. Besides, when a-Si is converted to P-Si by annealing with excimer laser to form the active layer 104, the buffer layer 102 further decrease heat dissipation between the P-Si active layer 104 and the substrate 100, and the effect of temperature rise on the substrate 100 during annealing is reduced.

[0052] As an example, the buffer layer 102 is made from silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer 102 has a thickness about 50-300 nm. For example, the buffer layer 102 is made from silicon oxide and has a thickness about 50-100 nm. Alternatively, the buffer layer 102 is made from silicon nitride and has a thickness about 100-300 nm. By forming the buffer layer on the substrate with the above thickness, it is possible to not only efficiently isolate impurities from the substrate, but also to protect the substrate during laser annealing.

[0053] As an example, the LTPS TFT is a top gate type TFT. For example, the active layer 104 is arranged on the buffer layer 102. The LTPS TFT further comprises an interlayer dielectric layer 112 which is arranged on the gate 110. The source 118 and the drain 120 are connected to the active layer 104, respectively, through vias which run through the graphene oxide layer 106, the gate insulating layer 108 and the interlayer dielectric layer 112. In particular, as shown in FIG. 1, the LTPS TFT comprises the substrate 100, a stack of the active layer 104 and the graphene oxide layer 106 which is formed on the substrate, the gate insulating layer 108 which covers the substrate 100 and the stack, the gate 110 which is formed on the gate insulating layer 108 and arranged over the stack, the interlayer dielectric layer 112 which covers the gate 110 and the gate insulating layer 108, and the source 118 and the drain 120 which are formed on the interlayer dielectric layer 112 and electrically connected to the active layer 104.

[0054] In the top gate type TFT, the active layer 104 is directly formed on the substrate 100. Since the substrate 100 has a very even surface, the active layer 104 which is formed on the substrate 100 also has a relatively even surface. This reduces the roughness of the interface between the active layer 104 and the gate insulating layer 108, and improves the performance of LTPS TFT.

[0055] The concept of present disclosure is also applicable to a bottom gate type TFT. Namely, the LTPS TFT is a bottom gate type TFT. For example, as shown in FIG. 3, a gate 204 is arranged on a buffer layer 202. The LTPS TFT further comprises an interlayer dielectric layer 212 which is arranged on an active layer 210. A source 214 and a drain 216 are connected to the active layer 210, respectively, through vias which run through the interlayer dielectric layer 212. In particular, as shown in the figure, the LTPS TFT comprises a substrate 200, and the gate 204, a gate insulating layer 206 which covers the substrate 200 and the gate 204, a stack of a graphene oxide layer 208 and the active layer 210 which is formed on the gate insulating layer 206, the interlayer dielectric layer 212 which covers the gate insulating layer 206 and the stack, and the source 214 and the drain 216 which are formed on the interlayer dielectric layer 212 and electrically connected to the active layer 210.

[0056] In the bottom gate type TFT, the gate 204 and the gate insulating layer 206 act as an optical protection layer for the active layer 210, and prevent the light from a back light source from irradiating on the photon-generated carriers from the active layer 210, which otherwise would impair the electrical characteristics of the active layer 210 and thus affect the performance of TFT.

[0057] As an example, as shown in FIG. 2, the active layer 104 comprises the doped source contact area 104S and drain contact area 104D. The source 118 is arranged over the source contact area 104S and connected to the source contact area 104S. The drain 120 is arranged over the drain contact area 104D and connected to the drain contact area 104D. For example, portions of the active layer 104 to which the source 118 and the drain 120 are to be connected are formed into the source contact area 104S and the drain contact area 104D, e.g., by doping. This realizes an ohmic contact between the source 118 and drain 120 and the active layer 104, so as to improve the performance of LTPS TFT.

[0058] According to a second aspect of the present disclosure, it is provided an array substrate. The array substrate comprises the LTPS TFT as described above, a planarization layer which covers the LTPS TFT, and a pixel electrode, wherein the pixel electrode is connected to the drain of the LTPS TFT through a via which runs through the planarization layer.

[0059] As shown in FIG. 4, the array substrate comprises a planarization layer 122 which is arranged on the LTPS TFT and a pixel electrode 124 which is arranged on the planarization layer 122. The planarization layer 122 is generally made from resin or other insulating materials, and is provided with a via which exposes the drain 120 of the TFT. The pixel electrode 124 is connected with the drain 120 of the LTPS TFT through the via. In the array substrate shown in FIG. 4, the LTPS TFT is a top gate type, e.g. the LTPS TFT shown in FIG. 1 or 2.

[0060] FIG. 5 shows an array substrate to which a bottom gate type LTPS TFT is applied. The array substrate comprises a planarization layer 218 which is arranged on the LTPS TFT and a pixel electrode 220 which is arranged on the planarization layer 218. The planarization layer 218 is provided with a via which exposes the drain 216 of the TFT. The pixel electrode 220 is connected with the drain 216 of the LTPS TFT through the via. In the array substrate shown in FIG. 5, the LTPS TFT is the LTPS TFT shown in FIG. 3.

[0061] The array substrate according to the present disclosure has same or similar beneficial effects as the LTPS TFT as described above, which are not repeated here for simplicity.

[0062] According to a third aspect of the present disclosure, it is provided a display panel, which comprises the array substrate as described above.

[0063] The display panel is a display panel for an active matrix liquid crystal display (AMLCD) or an active matrix organic light emitting diode (AMOLED).

[0064] The display panel according to the present disclosure has same or similar beneficial effects as the LTPS TFT as described above, which are not repeated here for simplicity.

[0065] According to a fourth aspect of the present disclosure, it is provided a display device, which comprises the array substrate as described above. The display device is any product or component with a display function like a mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, and navigator.

[0066] The display device according to the present disclosure has same or similar beneficial effects as the LTPS TFT as described above, which are not repeated here for simplicity.

[0067] According to a fifth aspect of the present disclosure, it is provided a method for fabricating an LTPS TFT. As shown in FIG. 6, the method comprises: step S100, forming on a substrate an active layer, a source, a drain, a gate, and a gate insulating layer which is arranged between the active layer and the gate; and step S200, forming a graphene oxide layer between the active layer and the gate insulating layer. Due to graphene oxide has a smaller molecular structure than P-Si, the roughness and interfacial defect density of the interface between the P-Si active layer and the gate insulating layer is further reduced, and the characteristics of LTPS TFT is increased. Besides, the gate insulating layer pre-cleaning process is not required during the process for fabricating the LTPS TFT, and this simplifies the fabricating process and reduces cost.

[0068] As an example, forming the graphene oxide layer comprises: preparing a graphene oxide dispersion; spin coating the graphene oxide dispersion on the active layer or the gate insulating layer; and baking the graphene oxide dispersion to form the graphene oxide layer. Hereby, the graphene oxide layer is formed by spin coating and baking which are simple and cost effective.

[0069] As an example, preparing the graphene oxide dispersion comprises: preparing graphene oxide by oxidizing graphite with an oxidizing agent; and dispersing the graphene oxide in a solvent to prepare the graphene oxide dispersion. Hereby, the precursor dispersion is prepared, so that the graphene oxide layer is formed by spin coating which is simple and cost effective.

[0070] As an example, the oxidizing agent is a mixed solution of potassium permanganate and concentrated sulfuric acid. As an example, the solvent is an ethanol aqueous solution with a volume percentage of 10%.

[0071] As an example, the method further comprises: after baking the graphene oxide dispersion to form the graphene oxide layer, performing chemical mechanical polishing on the graphene oxide layer. Hereby, after spin coating and baking, the graphene oxide layer is subject to chemical mechanical polishing. This further increases the surface evenness of the graphene oxide layer. This further improves the roughness of the interface between the active layer and the gate insulating layer and reduces interfacial state defect density.

[0072] A method for fabricating an LTPS TFT according to the present disclosure will be described hereinafter with reference to FIGS. 7A-7N.

[0073] The substrate 100 is cleaned. The substrate 100 is made from a transparent material like glass. An active layer precursor, e.g., an a-Si film, is formed on the substrate 100 by a film forming process like plasma enhanced chemical vapor deposition (PECVD). The a-Si film has a thickness about 40-50 nm. Then, the substrate 100 is transferred to a furnace at an elevated temperature for dehydrogenation, i.e., reducing the content of hydrogen in the a-Si film. Gengerally, the content of hydrogen is controlled to a range not more than 2%. Then, the a-Si film on the substrate 100 is subject to an excimer laser annealing (ELA), so that the a-Si film is converted into a P-Si film, thus forming the active layer 104. Then, channel doping is performed.

[0074] Optionally, prior to forming the a-Si film, the buffer layer 102 is formed on the substrate 100. The buffer layer 102 is made form one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The buffer layer 102 has a single layer structure or a multiple layer structure. For example, in case the buffer layer 102 is made from silicon oxide, it has a thickness about 50-100 nm. In case the buffer layer 102 is made from silicon nitride, it has a thickness about 100-300 nm. As a result of the above steps, the structure shown in FIG. 7A is obtained.

[0075] Then, graphene oxide is prepared. Graphene is prepared in the following manner. Natural flakes of graphite are used as a raw material. Potassium permanganate and concentrated sulfuric acid are used as the oxidizing agent. The raw material of graphite is put into the oxidizing agent for an oxidizing reaction. The duration of reaction is about 1.5 hr (hour), and graphene oxide is obtained. As used herein, the term “concentrated sulfuric acid” indicates an aqueous solution of H.sub.2SO.sub.4 with a concentration larger than 70%, and the concentration is defined as the weight percentage of H.sub.2SO.sub.4 in the aqueous solution of H.sub.2SO.sub.4.

[0076] The resulting graphene oxide is cleaned with water to a neutral state. An ethanol aqueous solution with a volume percentage of 10% is used as the solvent, graphene oxide is dispersed by ultrasonic wave, and the graphene oxide dispersion is obtained. For example, graphene oxide dispersion is uniformly applied onto the active layer 104 by spin coating. Then, the graphene oxide dispersion is bake to form the graphene oxide layer 106. By adjusting the concentration of the dispersion, the thickness of the graphene oxide layer 106 is controlled to about 10 nm. Optionally, after baking, the graphene oxide layer 106 is subject to chemical mechanical polishing to increase the surface evenness. As a result of the above steps, the structure shown in FIG. 7B is obtained.

[0077] Then, the patterned active layer 104 and graphene oxide layer 106 is formed by a first patterning process. In the context of the present disclosure, the patterning process comprises processes like photoresist coating, masking, exposing, developing, and etching. In particular, photoresist is coated on the structure shown in FIG. 7B, and masking, exposing and developing are performed to form a patterned photoresist layer 151, as shown in FIG. 7C. Then, by taking the photoresist layer 151 as a mask, the active layer 104 and the graphene oxide layer 106 are etched, and the photoresist layer 151 is peeled off to form a stack of the patterned the active layer 104 and graphene oxide layer 106, as shown in FIG. 7D.

[0078] Then, the gate insulating layer 108 is deposited by PECVD. The gate insulating layer 108 covers the stack of the active layer 104 and the graphene oxide layer 106 as well as the buffer layer 102, as shown in FIG. 7E.

[0079] Then, the gate metal layer 110 is deposited on the gate insulating layer 108 by sputtering, as shown in FIG. 7F.

[0080] Then, the gate 110 is formed by a second patterning process. In particular, photoresist is coated the structure shown in FIG. 7F, and masking, exposing and developing are performed to form a patterned photoresist layer 152, as shown in FIG. 7G. Then, by taking the photoresist layer 152 as a mask, the gate metal layer 110 is etched, and the photoresist layer 152 is peeled off to form the gate 110, as shown in FIG. 7H.

[0081] Then, the interlayer dielectric layer 112 is deposited by PECVD, as shown in FIG. 7I.

[0082] After depositing the interlayer dielectric layer 112, vias for the source and drain are formed by a third patterning process. In particular, photoresist is coated on the structure shown in FIG. 7I, and masking, exposing and developing are performed to form a patterned photoresist layer 153, as shown in FIG. 7J. Then, by taking the photoresist layer 153 as a mask, the interlayer dielectric layer 112 is etched, and vias 114 which run through the graphene oxide layer 106, the gate insulating layer 108 and the interlayer dielectric layer 112 are formed. Then, the photoresist layer 153 is peeled off, and the structure shown in FIG. 7K is obtained.

[0083] Then, a source/drain metal layer 116 is deposited on the structure shown in FIG. 7K by sputtering. The source/drain metal layer 116 not only covers the interlayer dielectric layer 112, but also fills the vias for the source and drain which are formed in the previous step, as shown in FIG. 7L.

[0084] Then, the source 118 and the drain 120 are formed by a fourth patterning process. In particular, photoresist is coated on the structure shown in FIG. 7L, and masking, exposing and developing are performed to form a patterned photoresist layer 154, as shown in FIG. 7M. Then, by taking the photoresist layer 154 as a mask, the source/drain metal layer 116 is etched, and the photoresist layer 154 is peeled off to form the source 118 and the drain 120, as shown in FIG. 7N.

[0085] The subsequent process steps are identical with those for a conventional LTPS TFT, and are not described herein in detail. Similarly, as for the bottom gate type TFT shown in FIG. 3, after forming the gate insulating layer 206, the graphene oxide layer and the active layer are formed by film forming processes, respectively, and the stack of patterned graphene oxide layer and active layer is formed by a patterning process. Reference can be made to the process shown in FIGS. 7A-7N for the remaining process steps, and thus the remaining process steps are not described herein in detail.

[0086] In the LTPS TFT of the present disclosure, a graphene oxide layer is added between the P-Si active layer and the gate insulating layer. As a result, the roughness and interfacial defect density of the interface between the P-Si active layer and the gate insulating layer is further reduced, and this increases the characteristics of LTPS TFT. Besides, the gate insulating layer pre-cleaning process is not required during the process for fabricating the LTPS TFT, and this simplifies the fabricating process and reduces cost.

[0087] Apparently, the person with ordinary skill in the art can make various modifications and variations to the present disclosure without departing from the spirit and the scope of the present disclosure. In this way, provided that these modifications and variations of the present disclosure belong to the scopes of the claims of the present disclosure and the equivalent technologies thereof, the present disclosure also intends to encompass these modifications and variations. For example, the structure of the LTPS TFT in the present disclosure is not limited to the top gate structure shown in FIGS. 1-2 and the bottom gate structure shown in FIG. 3, as long as a graphene oxide layer is arranged between the gate insulating layer and the active layer. In short, the protection scope of the present disclosure is defined by the appended claims.