The present invention is a plasma etching method comprising subjecting a silicon-containing film to plasma etching using a process gas, the process gas comprising a linear saturated fluorohydrocarbon compound represented by a formula (1), and a gaseous fluorine-containing compound (excluding the compound represented by the formula (1)) that functions as a fluorine radical source under plasma etching conditions, wherein x represents 3 or 4, y represents an integer from 5 to 9, and z represents an integer from 1 to 3. The present invention provides a plasma etching method that can selectively etch the silicon-containing film with respect to the mask, and form a hole or a trench having a good shape within a short time.

CxHyF.sub.z  (1)

Described herein is a technique capable of improving the productivity of manufacturing of a semiconductor device in a method of processing a film by repeating different processes. A method of manufacturing a semiconductor device may include: (a) loading a substrate into a process vessel; (b) forming a first layer by supplying a first gas into the process vessel by a gas supply unit while maintaining the substrate at a first temperature by a temperature control unit; and (c) forming a second layer different from the first layer by supplying a second gas different from the first gas into the process vessel by the gas supply unit while maintaining the substrate at a second temperature different from the second temperature by the temperature control unit.

An etching process method is provided that includes outputting a first high frequency power from a first high frequency power supply in a cryogenic temperature environment where the temperature of a substrate is controlled to be less than or equal to −35° C., supplying a sulfur fluoride-containing gas and a hydrogen-containing gas, generating a plasma from the supplied sulfur fluoride-containing gas and hydrogen-containing gas, and etching a laminated film made up of laminated layers of silicon-containing films having different compositions with the generated plasma.

Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.

An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

A method for processing a substrate includes positioning a silicon substrate in a deposition chamber. One or more intermediate layers are deposited on a surface of the silicon. The one or more intermediate layers can include strontium, which combines with the silicon to form strontium silicide. Alternatively, the one or more intermediate layers comprise germanium. A layer of amorphous strontium titanate is deposited on the one or more intermediate layers in a transient environment in which oxygen pressure is reduced while temperature is increased. The substrate is then exposed to an oxidizing and annealing atmosphere that oxidizes the one or more intermediate layers and converts the layer of amorphous strontium titanate to crystalline strontium titanate.

A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion, and the first dielectric layer is a single-layer structure. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.

Provided herein are processes for transferring high quality large-area graphene layers (e.g., single-layer graphene) to a flexible substrate based on preferential adhesion of certain thin metallic films to graphene followed by lamination of the metallized graphene layers to a flexible target substrate in a process that is compatible with roll-to-roll manufacturing, providing an environmentally benign and scalable process of transferring graphene to flexible substrates.