A semiconductor device includes: a first insulating film; an interconnect disposed in the first insulating film and containing copper, cobalt, nickel, or manganese; a second insulating film that includes a first portion connected to the interconnect and that contains silicon and nitrogen; a third insulating film including a second portion connected to the first portion; a first conductor disposed in the first portion and in contact with the interconnect; a film covering a side surface of the second portion and containing a metal or containing silicon and nitrogen; and a second conductor disposed in the second portion and in contact with the film.

A method of manufacturing a semiconductor device includes: receiving a semiconductor structure, the semiconductor structure including: a fin structure; a dummy gate across over the fin structure to define a channel region of the fin structure; and a dummy dielectric layer separating the channel region of the fin structure from the dummy gate; removing the dummy gate and the dummy dielectric layer to expose the channel region of the fin structure; and forming a doped interfacial layer covering the channel region of the fin structure, in which the doped interfacial layer includes a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.

Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

A method for producing a closed cavity on a substrate, including: a) forming a cavity surrounded by at least one block on a given face of a substrate, the cavity having an aspect ratio higher than a determined threshold; and b) depositing a closing layer on the at least one block surrounding the cavity, the aspect ratio of the cavity being such that in b), the closing layer does not entirely fill the cavity and an empty space in the cavity is maintained.

Provided are a thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device. The thin film transistor comprises: an active layer, an etch stop layer disposed on the active layer, an overcoating layer disposed on the etch stop layer, and a source electrode and a drain electrode disposed on the overcoating layer, wherein the overcoating layer comprises at least one of a conductive material layer, a non-transparent insulation layer and a non-transparent semiconductor layer, and the source electrode and the drain electrode are electrically connected with the active layer.

A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.

Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.

To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first to third oxide semiconductor films contain the same element. The second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film.

A method comprises transporting a first stream of a carrier gas to a delivery device that contains a liquid precursor compound. The method further comprises transporting a second stream of the carrier gas to a point downstream of the delivery device. The first stream after emanating from the delivery device and the second stream are combined to form a third stream, such that the dew point of the vapor of the liquid precursor compound in the third stream is lower than the temperature of the plumbing that transports the vapor to a CVD reactor or a plurality of CVD reactors. The flow direction of the first stream, the flow direction of the second stream and the flow direction of the third stream are unidirectional and are not opposed to each other.

A method includes: forming a dummy gate dielectric layer over a channel region of a fin structure; forming a dummy gate over the dummy gate dielectric layer; removing the dummy gate and a first portion of the dummy gate dielectric layer to expose the channel region of the fin structure; removing a first nanowire of the fin structure above a second nanowire of the fin structure to remain the second nanowire of the fin structure; forming an interfacial layer surrounding the second nanowire; forming a material layer comprising dopants over the interfacial layer; and performing an annealing process to drive the dopants of the material layer into the interfacial layer, thereby forming a doped interfacial layer surrounding the second nanowire.