A deposition device for providing a thin film on a substrate. The device comprises a material source for providing at least one first metallic element which does not re-evaporate substantially from the substrate under particular growth conditions, at least one second metallic element or metal based molecule which does re-evaporate substantially from the substrate under the same growth conditions, and a component suitable for forming an at least one first compound with the at least one first metallic element and an at least one second compound with the at least one second metallic element or metal based molecule. The device comprises a controller configured to control the growth conditions, and the amounts of the at least one first metallic element, the at least one second metallic element or metal based molecule, and the component so as to obtain a substantially stoichiometric thin film.

Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.

A peeling method of one embodiment of the present invention includes a first step of forming a first insulating layer over a substrate; a second step of forming a second insulating layer over the first insulating layer; a third step of forming a peeling layer over the second insulating layer; a fourth step of performing plasma treatment on a surface of the peeling layer; a fifth step of forming a third insulating layer over the peeling layer; a sixth step of performing heat treatment; and a seventh step of separating the peeling layer and the third insulating layer from each other. The first insulating layer and the third insulating layer each have a function of blocking hydrogen and for example, include a silicon nitride film or the like. The second insulating layer has a function of releasing hydrogen by heating and for example, includes a silicon oxide film.

The invention provides a method for passivation of various surfaces (metal, polymer, semiconductors) from external contaminants, and the functionalization of inert surfaces. The method of the invention can functionalize 2D semiconductor and other insert surfaces such as non-reactive metals, oxides, insulators, glasses, and polymers. The method includes formation of a monolayer, an ordered bilayer or an ordered multilayer of metal phthalocyanines (MPc). The invention also provides layer structure in a semiconductor device, the layer structure comprising one of an ordered monolayer, ordered bilayer or ordered multi-layer of metal phthalocyanine upon a surface, and one of an ALD deposited layer or 2D semiconductor on the one of a monolayer, ordered bilayer or ordered multi-layer of metal phthalocyanine.

An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, forming a high-κ dielectric layer directly on the semiconductor layer as formed, and annealing the semiconductor layer, the high-dielectric layer, and the substrate. The semiconductor layer is a Group III-V compound semiconductor.

The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

A spin on carbon composition, comprises: a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker reacts with the carbon backbone polymer to partially crosslink the carbon backbone polymer at a first temperature, and the second crosslinker reacts with the carbon backbone polymer to further crosslink the carbon backbone polymer at a second temperature higher than the first temperature. The first crosslinker is a monomer, oligomer, or polymer. The second crosslinker is a monomer, oligomer, or polymer. The first and second crosslinkers are different from each other. When either of the first crosslinker or the second crosslinker is a polymer, the polymer is a different polymer than the carbon backbone polymer.

A semiconductor device manufacturing method includes forming a ring-shaped rib at an outer circumferential edge of a semiconductor wafer by grinding a center of a back surface of the semiconductor wafer, so that the rib has a thickness greater than a thickness of the center of the semiconductor wafer, pasting a first protective film on the back surface of the semiconductor wafer, pasting a second protective film so as to cover an outer circumferential edge of the first protective film and an outer circumference of the rib, positioning the back surface of the semiconductor wafer so as to face a heating surface of a hot plate and directly heating the first protective film and the second protective film by using the hot plate, and performing a plating treatment on a surface of the semiconductor wafer.

In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.