Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.

A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.

A Schottky barrier diode (semiconductor device) includes at least: a semiconductor substrate of an N type (first conductivity type); a semiconductor portion (first portion) of a P type (second conductivity type) opposite to the N type, the semiconductor portion being formed on a part of a one main surface side of the semiconductor substrate; a metal portion (second portion) with conductivity formed on the one main surface of the semiconductor substrate so as to be electrically connected to a part of the P type semiconductor portion; and a high resistance portion (third portion) formed so as to be electrically connected to a part of the P type semiconductor portion and to be in contact with a side surface and a bottom surface connected thereto of the P type semiconductor portion.

A method of manufacturing a semiconductor light emitting device, including arranging a plurality of particles in a monolayer on a substrate, dry etching the plurality of particles arranged to provide a void between the particles in a condition IN which the particles are etched while the substrate is not substantially etched; and dry etching the substrate using the plurality of particles after the particle etching step as an etching mask, thereby forming an uneven structure on one surface of the substrate.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks.

The instant invention provides a process for making metal or metalloid dichalcogenides from a metal or metalloid and elemental chalcogen using magnetron sputtering. The process may comprise the steps of directing sputtering gas ions at a metal or metalloid target, reacting the ejected metal or metalloid atoms from the target surface with an elemental chalcogen vapor and assembling the metal or metalloid dichalcogenides on a substrate. It can be used to make thin films of the dichalcogenides which have a use in layered semiconductor devices. The process of the invention is suitable for upscaling to potentially make the films on a wafer level. Films on large areas with high uniformity have for instance been obtained utilizing the reaction of the metal or metalloid in an ambient of vaporized chalcogen under controlled conditions and with low growth rates. The process of the invention can be used to deposit two dimensional channels as part of field effect transistors. The materials made with the process in general can have a use in nanoelectronics as a catalyst, as a photo-detector, photovoltaic or photocatalyst.

A LED structure includes a support and a plurality of nanowires located on the support, where each nanowire includes a tip and a sidewall. A method of making the LED structure includes reducing or eliminating the conductivity of the tips of the nanowires compared to the conductivity of the sidewalls during or after creation of the nanowires.

Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.

In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

An epitaxial base is provided. The epitaxial base includes a substrate and a carbon nanotube layer. The substrate has an epitaxial growth surface and defines a plurality of grooves and bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer attached on top surface of the bulges, and a second part of the carbon nanotube layer attached on bottom surface and side surface of the grooves.