An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.

Disclosed herein are a III-N semiconductor structure manufactured by growing a III-N material on a superlattice structure layer, formed of AlGaN and InAlN materials, which serves as a buffer layer, and a method for manufacturing the same. The disclosed III-N semiconductor structure includes: a substrate including a silicon material; a seed layer formed on the substrate and including an aluminum nitride (AlN) material; a superlattice structure layer formed by sequentially depositing a plurality of superlattice units on the seed layer; and a cap layer formed on the superlattice structure layer and including a gallium nitride (GaN) material, wherein the superlattice units are each composed of a first layer including an AlxGa1-xN wherein 0≤x≤1 and a second layer including an InyAl1-yN wherein 0y≤0.4.

A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

A method of forming a gallium oxide film is provided, and the method may include supplying mist of a material solution comprising gallium atoms and chlorine atoms to a surface of a substrate while heating the substrate so as to form the gallium oxide film on the surface of the substrate, in which a molar concentration of chlorine in the material solution is equal to or more than 3.0 times and equal to or less than 4.5 times a molar concentration of gallium in the material solution.

Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

The present invention provides a semiconductor device, comprising: a substrate (10); a stack of III-nitride transition layers (11) disposed on the substrate (10), the stack of III-nitride transition layers (11) maintaining an epitaxial relationship to the substrate (10); a first III-nitride layer (121) disposed on the stack of III-nitride transition layers (11); and a second III-nitride layer (122) disposed on the first III-nitride layer (121), the second III-nitride layer (122) having a band gap energy greater than that of the first III-nitride layer (121), wherein the stack of III-nitride transition layers (11) comprises a first transition layer (111), a second transition layer (112) on the first transition layer (111), and a third transition layer (113) on the second transition layer (112), and wherein the second transition layer (112) has a minimum aluminium molar ratio among the first transition layer (111), the second transition layer (112) and third transition layer (113). The present invention also relates to a method of forming such semiconductor device. The semiconductor device according to the present invention advantageously has a dislocation density less than or equal to 1×10.sup.9 cm.sup.−2 in the first III-nitride layer (121).

Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

A method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a SiC single crystal substrate, the method including identifying a total number of large-pit defects caused by micropipes in the SiC single crystal substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, using microscopic and photoluminescence images. Also disclosed is a method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, the method including identifying locations of the large-pit defects caused by micropipes in the SiC single crystal substrate and the large-pit defects caused by substrate carbon inclusions in the SiC epitaxial layer, using microscopic and photoluminescence images.

A method of manufacturing a silicon carbide epitaxial substrate includes: preparing a silicon carbide single-crystal substrate having a polytype of 4H and having a principal surface inclined at an angle θ from a {0001} plane in a <11-20> direction; growing a silicon carbide epitaxial layer on the principal surface having a basal plane dislocation, the basal plane dislocation having a portion extending in a <1-100> direction and a portion extending in a <11-20> direction; and irradiating the silicon carbide epitaxial layer with an ultraviolet light having a predetermined power and a predetermined wavelength for a predetermined period of time to stabilize the basal plane dislocation. After the irradiating, the basal plane dislocation does not move even when the basal plane dislocation is irradiated with an ultraviolet light having a power of 270 mW and a wavelength of 313 nm for 10 seconds.

A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions. Each of the protrusions includes a tip and a plurality of facets converging at the tip, and adjacent facets of adjacent protrusions are in contact with each other,