A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

There is provided a group III nitride semiconductor substrate (free-standing substrate (30)) that is formed of a group III nitride semiconductor crystal and has a thickness of 300 m or more and 1000 m or less. Both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes. A difference in a half width of an X-ray rocking curve (XRC) measured by making X-rays incident on each of the first and second main surfaces in parallel to an m axis of the group III nitride semiconductor crystal is 500 arcsec or less.

In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.

The invention relates to a micro cantilever beam sensor and making method, including a chip, and its character: there is at least a group of sensor cells set on the chip, where the sensor cell is composed of the completely same four force-sensitive resistors composing a Wheatstone bridge and two cantilever beams, two of these resistors are on the substrate of the chip, the other two are on the two cantilever beams, respectively, one cantilever beam acts on a measuring cantilever beam and the other one acts on a reference cantilever beam, and the measuring cantilever beam is set with a sensitive layer on the surface. It can design and prepare in a liquid-flow micro-tank by front etching and silicon-glass bonding techniques, to directly detect liquid biomolecule. Whether applied to gas sensor or biosensor, it will play an important role in reducing device size, enhancing device sensitivity and realizing sensor multi-functionality. It has wide prospects for the fields of environment monitoring, clinic diagnosis and therapy, new drug development, food safety, industrial processing control, military and so on.

The present disclosure provides a method and structure for producing large area gallium and nitrogen engineered substrate members configured for the epitaxial growth of layer structures suitable for the fabrication of high performance semiconductor devices. In a specific embodiment the engineered substrates are used to manufacture gallium and nitrogen containing devices based on an epitaxial transfer process wherein as-grown epitaxial layers are transferred from the engineered substrate to a carrier wafer for processing. In a preferred embodiment, the gallium and nitrogen containing devices are laser diode devices operating in the 390 nm to 425 nm range, the 425 nm to 485 nm range, the 485 nm to 550 nm range, or greater than 550 nm.

Photonic devices having Al.sub.1-xSc.sub.xN and Al.sub.yGa.sub.1-yN materials, where Al is Aluminum, Sc is Scandium, Ga is Gallium, and N is Nitrogen and where 0<x0.45 and 0y1.

Structures having an epitaxial metal layer, a semiconductor layer, or both, may be formed as part of a first process in a first chamber, and then undergo subsequent processing in a second chamber. A modified device may be formed from a pre-formed device by application of further layers in a second process. One or more layers may be formed directly over the device, formed directly over a seed layer formed over the device, or formed over a substrate that is subsequently bonded and partially cleaved from the device. A seed layer may include a lattice constant transition, chemical transition, or other suitable transition between the device and an epitaxial layer. A cleave layer may include a porous layer configured to fracture at a relatively lower shear loading than the rest of the structure, thus providing a predictable separation plane.

A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions containing carbon, phosphorus, and hydrogen as constituent elements to form a modified layer that is located in a surface layer portion of the semiconductor wafer and that contains the constituent elements of the cluster ions as a solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The ratio y/x of the number y of the phosphorus atoms with respect to the number x of the carbon atoms satisfies 0.5 or more and 2.0 or less, where the number of atoms of carbon, phosphorus, and hydrogen in the cluster ions is expressed by C.sub.xP.sub.yH.sub.z (x, y, and z are integers each equal to or more than 1).

An electrical connection is formed between first and second conductive elements, by inserting a nano-metal material between the first and second conductive elements; and heating the nano-metal material to a melting temperature to form the electrical connection between the first and second conductive elements. The nano-metal material may comprise a nano-metal paste or ink comprised of one or more of Gold (Au), Copper (Cu), Silver (Ag), and/or Aluminum (Al) nano-particles that melt or fuse into a solid to form the electrical connection, at a melting temperature of about 150-250 degrees C., and more preferably, about 175-225 degrees C. The electrical connection may be formed between a solar cell and a substrate by creating a via in the solar cell between a front and back side of the solar cell, wherein the via is connected to a contact on the front side of the solar cell and a trace on the substrate.