The present disclosure provides a method and structure for producing large area gallium and nitrogen engineered substrate members configured for the epitaxial growth of layer structures suitable for the fabrication of high performance semiconductor devices. In a specific embodiment the engineered substrates are used to manufacture gallium and nitrogen containing devices based on an epitaxial transfer process wherein as-grown epitaxial layers are transferred from the engineered substrate to a carrier wafer for processing. In a preferred embodiment, the gallium and nitrogen containing devices are laser diode devices operating in the 390 nm to 425 nm range, the 425 nm to 485 nm range, the 485 nm to 550 nm range, or greater than 550 nm.

A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 110.sup.21 atoms/cm.sup.3 or greater.

A method for direct growth of a patterned transition metal dichalcogenide monolayer, the method including the steps of providing a substrate covered by a mask, the mask having a pattern defined by one or more shaped voids; thermally depositing a salt on the substrate through the one or more shaped voids such that a deposited salt is provided on the substrate in the pattern of the mask; and thermally co-depositing a transition metal oxide and a chalcogen onto the deposited salt to form the patterned transition metal dichalcogenide monolayer having the pattern of the mask. Also provided is a patterned transition metal dichalcogenide monolayer prepared according to the method.

A semiconductor structure includes a substrate; a nucleation layer located above the substrate; and a metal nitride thin film located between the nucleation layer and the substrate. A diffusion of atoms in a material of the substrate is suppressed by depositing the metal nitride thin film between the substrate and the nucleation layer, so that a thickness of the nucleation layer is significantly reduced, and a total thermal resistance of the semiconductor structure is reduced.

The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.

A polycrystalline material having low mechanical strain is provided. The polycrystalline material includes one or multiple layers of a first type and one or multiple layers of a second type. The layers of the first type and the layers of the second type each include at least one polycrystalline material component. The layers of the first type have a smaller average crystal grain size than the layers of the second type, a layer of the first type and a layer of the second type being situated, at least in part, one above the other in an alternating sequence, and it being the case for the transition between the layers of the first type and the layers of the second type to be abrupt or continuous.

A method of growing patterns of an atomic layer of metal dichalcogenides, the method including providing a substrate, providing aligned patterns of carbon nanostructures on the substrate, providing a first metal portion in contact with a first portion of the patterns of carbon nanostructures and a second metal portion in contact with a second portion of the patterns of carbon nanostructures, depositing a salt layer on the substrate and the patterns of carbon nanostructures, resistively heating the patterns of carbon nanostructures to remove the patterns of carbon nanostructures and salt deposited thereon from the substrate, wherein removing the patterns of carbon nanostructures and salt deposited thereon from the substrate provides salt patterns on the substrate, and growing an atomic layer of metal dichalcogenides on the salt patterns, wherein the atomic layer of metal dichalcogenides is provided in aligned patterns each having a pre-defined width. Also disclosed are patterns of an atomic layer of metal dichalcogenides prepared according to the method of the disclosure.

An electrical connection is formed between first and second conductive elements, by inserting a nano-metal material between the first and second conductive elements; and heating the nano-metal material to a melting temperature to form the electrical connection between the first and second conductive elements. The nano-metal material may comprise a nano-metal paste or ink comprised of one or more of Gold (Au), Copper (Cu), Silver (Ag), and/or Aluminum (Al) nano-particles that melt or fuse into a solid to form the electrical connection, at a melting temperature of about 150-250 degrees C., and more preferably, about 175-225 degrees C. The electrical connection may be formed between a solar cell and a substrate by creating a via in the solar cell between a front and back side of the solar cell, wherein the via is connected to a contact on the front side of the solar cell and a trace on the substrate.

A semiconductor device includes a porous silicon layer on a silicon substrate. The semiconductor device also includes a seal layer on the porous silicon layer. The semiconductor device further includes a high charge carrier mobility material layer on the seal layer. The semiconductor device may further include a strain balancing intermediate layer between the seal layer and the high charge carrier mobility material layer. Different high charge carrier mobility materials can be used in the high charge carrier mobility material layer to form different semiconductor devices.

A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.