A crystal substrate 1 includes an underlying layer 2 and a thick film 3. The underlying layer 2 is composed of a crystal of a nitride of a group 13 element and includes a first main face 2a and a second main face 2b. The thick film 3 is composed of a crystal of a nitride of a group 13 element and provided over the first main face of the underlying layer. The underlying layer 2 includes a low carrier concentration region 5 and a high carrier concentration region 4 both extending between the first main face 2a and the second main face 2b.

A transistor includes a channel layer, a gate stack, and source/drain regions. The channel layer includes a graphene layer and hexagonal boron nitride (hBN) flakes dispersed in the graphene layer. Orientations of the hBN flakes are substantially aligned. The gate stack is over the channel layer. The source/drain regions are aside the gate stack.

A method of manufacturing a semiconductor device includes forming a first AlN layer on a first main surface of a single-crystal substrate, partly etching the first AlN layer to form a plurality of pieces of AlN seed crystals on the first main surface from the first AlN layer, and forming a second AlN layer on the first main surface using the AlN seed crystals as growth nuclei.

A multilayer semiconductor structure of the present disclosure includes a substrate a buffer layer disposed on the substrate and a semiconductor layer disposed on the buffer layer. A void is provided between the buffer layer and the semiconductor layer.

Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

Generally, examples described herein relate to methods and semiconductor processing systems for anisotropically epitaxially growing a material on a silicon germanium (SiGe) surface. In an example, a surface of silicon germanium is formed on a substrate. Epitaxial silicon germanium is epitaxially grown on the surface of silicon germanium. A first growth rate of the epitaxial silicon germanium is in a first direction perpendicular to the surface of silicon germanium, and a second growth rate of the epitaxial silicon germanium is in a second direction perpendicular to the first direction. The first growth rate is at least 5 times greater than the second growth rate.

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

Disclosed are a semiconductor structure and a method for preparing the same, relating to the field of semiconductor technologies. The semiconductor structure includes: a substrate; and a plurality of functional film layers stacked on the substrate, the plurality of functional film layers include a first semiconductor layer and a second semiconductor layer stacked with each other, the first semiconductor layer is arranged between the substrate and the second semiconductor layer. The first semiconductor layer includes a plurality of defect pits recessed toward the substrate, the defect pits are filled by the second semiconductor layer, and one side of the second semiconductor layer away from the first semiconductor layer is a plane. The semiconductor structure and the preparation method thereof provided in the present application solve the problem of vertical leakage in the semiconductor structure in the prior art.

A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.