Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.

A method for producing a substantially planar surface for semiconductor processing to improve lithography, planarization, and other process steps that benefit from a flat substrate. The method includes depositing a first alloy to form a first layer on a substrate. The first layer has a center high deposition, meaning the height in the center of the substrate is higher than the height at the edges of the substrate. The method further includes depositing a second alloy on the first layer to form a second layer. The first alloy has a different composition than the second alloy. In such a method the net deposition is substantially planar reducing or eliminating deposition induced long-range distortions that might occur across a substrate.

Provided is a thin film transistor including a highly-textured dielectric layer, an active layer, a gate electrode and a source/drain electrode that are stacked on a base substrate. The source/drain electrode includes a source electrode and a drain electrode. The gate electrode and the active layer are insulated from each other. The source electrode and the drain electrode are electrically connected to the active layer. Constituent particles of the active layer are of monocrystalline silicon-like structures. According to the present disclosure, the highly-textured dielectric layer is adopted to replace an original buffer layer to induce the active layer to grow into a monocrystalline silicon-like structure, such that the performance of the thin film transistor is improved.

A masking member contains parallel through-holes, each of the through-holes contains a tilted wall structure; an upper end of the tilted wall structure of one of the through-holes abuts on an upper end of the tilted wall structure of an adjacent one of the through-holes thereby forming a knife-edge ridge at the upper ends. The masking member may in contact with a substrate. Formation in quantity of various different populations of a substance being studied with multiple combinations of distribution form and distribution density may be conducted by dripping a suspension of a single concentration of the substance onto the masking member.

A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.

A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; bonding a first side of the silicon carbide wafer to the carrier wafer; splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting; and forming a graphene material on the silicon carbide layer.

A crystal growth method of the present disclosure includes: preparing a substrate having a surface layer; forming a mask pattern including a plurality of strip bodies on the surface layer to separate the surface layer into segments by the plurality of strip bodies and expose part of the surface layer; and forming, on a plurality of growth regions constituted by the exposed part of the surface layer, a crystal growth-derived layer by causing a semiconductor crystal which differs in lattice constant from the substrate to grow by a vapor-phase growth process. Each of the plurality of strip bodies has side faces inclined so that a width between the side faces gradually decreases with distance from the surface layer.

A material structure for silicon-based gallium nitride microwave and millimeter-wave devices and a manufacturing method thereof are provided. The material structure includes: a silicon substrate; a dielectric layer of high thermal conductivity, disposed on an upper surface of the silicon substrate, and an uneven first patterned interface being formed between the dielectric layer and the silicon substrate; a buffer layer, disposed on an upper surface of the dielectric layer, and an uneven second patterned interface being formed between the buffer layer and the dielectric layer; a channel layer, disposed on an upper surface of the buffer layer; and a composite barrier layer, disposed on an upper surface of the channel layer. In the material structure, the uneven patterned interfaces increase contact areas of the interfaces, a thermal boundary resistance and a thermal resistance of device are reduced, and a heat dissipation performance of device is improved.

A method for forming a silicon film includes supplying a first processing gas including a silicon-containing gas to a substrate to deposit a first silicon film under a first processing condition; and supplying a second processing gas including the silicon-containing gas to the substrate to deposit a second silicon film under a second processing condition. A second in-plane distribution of film characteristic when the second silicon film is deposited under the second processing condition is different from a first in-plane distribution of the film characteristic when the first silicon film is deposited under the first processing condition.