The invention relates to a method for the production of a light-emitting diode, characterized in that the method comprises a step of preparing a light-emitting layer (20) on a front face of a support (10), said emitting layer comprising at least two adjacent quantum wells (21, 22, 23) emitting at different wavelengths, said quantum wells (21, 22, 23) being in contact with the front face of the support. According to the invention, the step in which the light-emitting layer is deposited comprises a sub-step consisting in locally varying the temperature of a rear face of the support opposite the front face such that the front face of the support comprises at least two zones at different temperatures.

The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench. The silicon-on-insulator layer is still shrinks after the bulk silicon region trench is formed, as the result, there is no bump on the surface of the silicon-on-insulator layer, thus the process window becomes controllable.

A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

According to one embodiment, a semiconductor device is provided with a first single crystal layer, a polycrystalline layer provided on an entire surface of the first single crystal layer, and a second single crystal layer bonded to the polycrystalline layer. The coefficient of thermal expansion of the polycrystalline layer is greater than the coefficient of thermal expansion of the second single crystal layer, and is smaller than the coefficient of thermal expansion of a compound semiconductor layer which can be provided on the second single crystal layer using an intervening a buffer layer.

A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

Described herein are devices and methods for facet suppression in spalling of (100) GaAs by redirecting the fracture front along features created by buried nanoimprint lithography (NIL)-patterned SiO.sub.2. Successful facet suppression using patterns that result in favorable fracture along the SiO.sub.2/GaAs interface and/or through voids formed above the pattern in the coalesced layer is provided. These results allow for the design of patterns that would successfully interrupt the fracture front and suppress faceting that, combined with growth optimization, define a path forward for this technology to be used as a way to reduce the need for repreparation of the (100) GaAs substrate surface after spalling.

A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.

Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.

Methods for depositing a silicon-germanium film on a substrate are described. The method comprises exposing a substrate to a silicon precursor and a germanium precursor to form a conformal silicon-germanium film. The substrate comprises at least one film stack and at least one feature, the film stack comprising alternating layers of silicon and silicon-germanium. The silicon-germanium film has a conformality greater than 50%.

Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).