Exemplary deposition methods may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. The method may include striking a plasma in the processing region between a faceplate and a pedestal of the semiconductor processing chamber. The pedestal may support a substrate including a patterned photoresist. The method may include maintaining a temperature of the substrate less than or about 200° C. The method may also include depositing a silicon-containing film along the patterned photoresist.

A method includes flowing a carbon-containing precursor and a carrier gas into a processing volume having a substrate positioned therein, generating a plasma in the processing volume by applying a first RF bias to a substrate support to deposit a first portion of carbon film onto the substrate, and terminating flow of the carbon-containing precursor while maintaining flow of the carrier gas to maintain the plasma within the processing volume. The method also includes flowing a nitrogen-containing gas into the processing volume and ionizing the nitrogen-containing gas in the presence of the plasma, exposing the substrate having the carbon film thereon to the ionized nitrogen-containing gas for a time period less than three seconds, and terminating flow of the nitrogen-containing gas while maintaining the plasma and reintroducing the carbon-containing precursor into the processing volume in the presence of the plasma to deposit a second portion of the carbon film.

Compounds and method of preparation of Si—X and Ge—X compounds (X═N, P, As and Sb) via dehydrogenative coupling between the corresponding unsubstituted silanes and amines (including ammonia) or phosphines catalyzed by metallic catalysts is described. This new approach is based on the catalytic dehydrogenative coupling of a Si—H and a X—H moiety to form a Si—X containing compound and hydrogen gas (X ═N, P, As and Sb). The process can be catalyzed by transition metal heterogenous catalysts such as Ru(0) on carbon, Pd(0) on MgO) as well as transition metal organometallic complexes that act as homogeneous catalysts. The —Si—X products produced by dehydrogenative coupling are inherently halogen free. Said compounds can be useful for the deposition of thin films by chemical vapor deposition or atomic layer deposition of Si-containing films.

A method for protecting a semiconductor film comprised of one or more layers during processing. The method includes placing a surface of the semiconductor film in direct contact with a surface of a protective covering, such as a separate substrate piece, that forms an airtight or hermetic seal with the surface of the semiconductor film, so as to reduce material degradation and evaporation in the semiconductor film. The method includes processing the semiconductor film under some conditions, such as a thermal annealing and/or controlled ambient, which might cause the semiconductor film's evaporation or degradation without the protective covering.

A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H—SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 6.0 inclusions/cm.sup.2, and wherein a density of large pit defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.5 defects/cm.sup.2 or less.

Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and an IGZO fin formed above the substrate. Embodiments may include a source contact and a drain contact that are formed adjacent to more than one surface of the IGZO fin. Additionally, embodiments may include a gate electrode formed between the source contact and the drain contact. The gate electrode may be separated from the IGZO layer by a gate dielectric. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.

Compounds and method of preparation of Si—X and Ge—X compounds (X═N, P, As and Sb) via dehydrogenative coupling between the corresponding unsubstituted silanes and amines (including ammonia) or phosphines catalyzed by metallic catalysts is described. This new approach is based on the catalytic dehydrogenative coupling of a Si—H and a X—H moiety to form a Si—X containing compound and hydrogen gas (X═N, P, As and Sb). The process can be catalyzed by transition metal heterogenous catalysts such as Ru(0) on carbon, Pd(0) on MgO) as well as transition metal organometallic complexes that act as homogeneous catalysts. The —Si—X products produced by dehydrogenative coupling are inherently halogen free. Said compounds can be useful for the deposition of thin films by chemical vapor deposition or atomic layer deposition of Si-containing films.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.