Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

A method of forming a semiconductor structure includes providing a to-be-etched layer, forming a core layer over the to-be-etched layer, the core layer including a first trench extending along a first direction, forming a sidewall spacer layer on a top surface of the core layer and on sidewalls and a bottom surface of the first trench, forming a block cut structure in the first trench after forming the sidewall spacer layer, and after forming the block cut structure, etching back the sidewall spacer layer until exposing the top surface of the core layer, thereby leaving a sidewall spacer on the sidewalls of the first trench. The block cut structure extends through the first trench along a second direction. The second direction and the first direction are different. The block cut structure includes a first block-cut layer and a second block-cut layer.

A semiconductor structure and a method for forming the same are provided. The method includes: providing a base, a pattern transfer material layer being formed above the base; performing first ion implantation, to dope first ions into the pattern transfer material layer, to form first doped mask layers arranged in a first direction; forming first trenches in the pattern transfer material layer on two sides of the first doped mask layer in a second direction, to expose side walls of the first doped mask layer; forming mask spacers on side walls of the first trenches; performing second ion implantation, to dope second ions into some regions of the pattern transfer material layer that are exposed from the first doped mask layers and the first trenches, to form second doped mask layers; removing the remaining pattern transfer material layer, to form second trenches; and etching the base along the first trenches and the second trenches, to form a target pattern. The present disclosure improves the accuracy of pattern transfer.

A tool and method for processing substrates by encapsulating a mask to protect from degradation during an etch-back to prevent a feature liner material from pinching off an opening during deposition-etch cycles used to fabricate high aspect ratio features with very tight critical dimension control.

Provided is a film for application to a 3D sample, the film including a photoresist layer that has alignment or direction marks thereon. After the fine pattern of the photoresist layer or coat is exposed, the photoresist layer is applied to a desired position of the 3D sample by aligning the alignment or direction marks of the film with alignment or direction marks on the 3D sample. This allows for transfer of an appropriate fine pattern. Part or all of the thickness or area of the photoresist layer is developed to form projections or depressions in the photoresist layer before the film is applied to the 3D sample.

A DRAM includes a substrate, a plurality of first active regions disposed on the substrate and arranged end-to-end along the first direction, and a plurality of second active regions disposed between the first active regions and arranged end-to-end along the first direction. The second active regions respectively have a first sidewall adjacent to a first trench between the second active region and one of the first active regions and a second sidewall adjacent to a second trench between the ends of the first active regions, wherein the second sidewall is taper than the first sidewall in a cross-sectional view.

A method includes providing a substrate including mandrels of a first material positioned on an underlying layer. Each of the mandrels includes a first sidewall and an opposing second sidewall. The method further includes forming sidewall spacers made of a second material and including a first sidewall spacer abutting each respective first sidewall and a second sidewall spacer abutting each respective second sidewall. The mandrels extend above top surfaces of the sidewall spacers. The method also includes forming first capped sidewall spacers by depositing a third material on the first sidewall spacers without depositing on the second sidewall spacers, forming second capped sidewall spacers by depositing a fourth material on the second sidewall spacers without depositing on the first sidewall spacers, and selectively removing at least one of the first material, the second material, the third material, and the fourth material to uncover an exposed portion of the underlying layer.

A technique for suppressing a metal component from remaining at a bottom of a mask pattern when the mask pattern is formed using a metal-containing resist film. A developable anti reflection film 103 is previously formed below a resist film 104. Further, after exposing and developing the wafer W, TMAH is supplied to the wafer W to remove a surface of the anti-reflection film 103 facing a bottom of the recess pattern 110 of the resist film 104. Therefore, the metal component 105 can be suppressed from remaining at the bottom of the recess pattern 110. Therefore, when the SiO.sub.2 film 102 is subsequently etched using the pattern of the resist film 104, the etching is not hindered, so that defects such as bridges can be suppressed.

Exemplary methods of semiconductor processing may include etching one or more features partially through a dielectric material to expose material from one or more layer pairs formed on a substrate. The methods may include halting the etching prior to penetrating fully through the dielectric material, and prior to exposing material from all layer pairs formed on the substrate. The methods may include forming a layer of carbon-containing material on the exposed material from each of the one or more layer pairs having exposed material. The methods may include etching the one or more features fully through the dielectric material to expose material for each remaining layer pair formed on the substrate.

Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.