Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

Embodiments are described herein to reshape spacer profiles to improve spacer uniformity and thereby improve etch uniformity during pattern transfer associated with self-aligned multiple-patterning (SAMP) processes. For disclosed embodiments, cores are formed on a material layer for a substrate of a microelectronic workpiece. A spacer material layer is then formed over the cores. Symmetric spacers are then formed adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps. For one example embodiment, one or more oblique physical vapor deposition (PVD) processes are used to deposit the additional spacer material for the spacer profile reshaping. This reshaping of the spacer profiles allows for symmetric spacers to be formed thereby improving etch uniformity during subsequent pattern transfer processes.

Aspects of this disclosure relate to selective removal of material of a layer, such as a carbon-containing layer. The layer can be over a patterned structure of two different materials. Treating the layer to cause the removal agent to be catalytically activated by a first area of the patterned structure to remove material of the organic material over the first area at a greater rate than over a second area of the patterned structure having a different composition from the first area.

A semiconductor device includes a lower structure, a first interlayer dielectric (ILD) on the lower structure, first pattern regions extending inside the first ILD in a first direction, the first pattern regions being spaced apart from each other in a second direction perpendicular to the first direction, each of the first pattern regions including at least one first pattern, and both ends of the at least one first pattern in the first direction being concave, and second pattern regions extending inside the first ILD in the first direction, the second pattern regions being spaced apart from each other in the second direction and alternating with the first pattern regions in the second direction, and each of the second pattern regions including at least one second pattern.

A method of manufacturing a semiconductor device includes forming a first resist layer over a substrate, and forming a second resist layer over the first resist layer. The second resist layer is patterned to expose a portion of the first resist layer to form a second resist layer pattern. The first resist layer is exposed to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern. Portions of the first resist layer exposed to the XUV radiation diffracted by the second resist layer are removed.

A method for preparing a semiconductor device is provided. The method for preparing the semiconductor device includes: providing a substrate, and forming a first dielectric layer on one side of the substrate, where the substrate includes an array area and a peripheral area arranged outside of the array area; forming an initial mask pattern on one side of the first dielectric layer away from the substrate; performing at least two patterning processes on the initial mask pattern, to form a first mask pattern in the array area and to form a second mask pattern in the peripheral area. The first mask pattern has a first height, the second mask pattern has a second height, and the second height is greater than the first height. Both of the array area and the peripheral area are exposed by using each of the at least two patterning processes.

Disclosed herein is a method for forming metal-oxides in the photoresist to improve profile control. The method includes infiltrating a metal oxide in a photoresist layer by pressurizing a methyl-containing material in a processing environment proximate a film stack. The film stack includes the photoresist layer, the photoresist layer being disposed on top of and in contact with an underlayer. The underlayer disposed on top of a substrate. The method includes etching the film stack including the photoresist layer implanted with the metal oxide.

Equipment for coating a wafer is disclosed, where the equipment includes a wafer holder configured to spin the wafer while holding the wafer; a rotary drive configured to spin the wafer holder; a nozzle configured to pour liquid onto a surface to be coated of the wafer; an annular duct disposed circumferentially around the wafer when the wafer is spun by the wafer holder, the duct configured to collect material ejected off an edge of the wafer; and an air knife disposed proximate a backside, the backside being opposite the side to be coated, where the air knife is configured to blow an air curtain through a slot onto an exposed edge region of the backside at a grazing angle of incidence to flow gas radially outward along the backside toward the annular duct.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an intermediate semiconductor structure; etching a part of the mandrel layer, exposing a part of the polycrystalline silicon layer, and forming a first spacing group; depositing a first spacing layer, and covering the first spacing group and an exposed area of the polycrystalline silicon layer; removing the first spacing group and a part of the first spacing layer, exposing a part of the polycrystalline silicon layer, and forming a second spacing group; depositing a second spacing layer, and covering the second spacing group and an exposed area of the polycrystalline silicon layer; removing the second spacing group and a part of the second spacing layer, exposing a part of the polycrystalline silicon layer, and forming a third spacing group.

Embodiments provide method for forming a connecting pad. The method includes: providing a substrate; sequentially forming a conductive layer, a first pattern definition layer and a second pattern definition layer on a surface of the substrate; sequentially forming three groups of patterns intersecting with each other at 120° on the second pattern definition layer, an intersection portion of the three groups of patterns forming a hexagonal pattern definition structure on the second pattern definition layer; transferring the pattern definition structure downward, and etching away a portion of the first pattern definition layer, such that the remaining first pattern definition layer forms a columnar structure, wherein a bottom of the columnar structure is circular in shape under an action of an etching load effect; and etching the conductive layer by using the remaining first pattern definition layer as a mask, such that the remaining conductive layer forms a circular connecting pad.