A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Embodiments are described herein that apply capping layers to cores prior to spacer formation in self-aligned multiple patterning (SAMP) processes to achieve vertical spacer profiles. For one embodiment, a plasma process is used to deposit a capping layer on cores, and this capping layer causes resulting core profiles to have protective caps. These protective caps formed with the additional capping layer help to reduce or minimize material loss and corner loss of the core material during spacer deposition and spacer etch processes. This reduction in core material loss improves the resulting spacer profile so that a more vertical profile is achieved. For one embodiment, an angle of 80-90 degrees is achieved for vertical sidewalls of the spacers adjacent core sites with respect to the horizontal surface of the underlying layer, such as a hard mask layer formed on a substrate for a microelectronic workpiece.

A semiconductor structure and a forming method thereof are provided. In one form, a forming method includes: providing a base; forming a mandrel layer extending along a first direction; forming a mask spacer on a side wall of the mandrel layer; forming a first segmentation layer extending along a second direction, where the first segmentation layer is in contact with a side wall of the mask spacer along the first direction; forming a sacrificial layer arranged spaced from the mandrel layer along the second direction, where the sacrificial layer covers the side wall of the mask spacer along the first direction, and along the first direction, the sacrificial layer protrudes from two sides of the first segmentation layer and covers a part of a side wall of the first segmentation layer; forming a planarization layer on the base exposed from the sacrificial layer, the mandrel layer, the mask spacer, and the first segmentation layer; removing the sacrificial layer to form a first groove, where the first groove is segmented by the first segmentation layer along the first direction; removing the mandrel layer to form a second groove; and patterning a target layer below the first groove and the second groove by using the mask spacer, the first segmentation layer, and the planarization layer as a mask to form a target pattern. Embodiments and implementations of the present disclosure help to improve pattern precision and pattern quality of a target pattern.

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

The object is to provide a mask blank substrate, a mask blank, and a transfer mask which can achieve easy correction of a wavefront by a wavefront correction function of an exposure apparatus. The further object is to provide methods for manufacturing them.

A virtual surface shape, which is an optically effective flat reference surface shape defined by a Zernike polynomial, is determined, wherein the Zernike polynomial is composed of only terms in which the order of variables related to a radius is second or lower order and includes one or more terms in which the order of the variables related to a radius is second-order; and the mask blank substrate, in which difference data (PV value) between the maximum value and the minimum value of difference shape between a virtual surface shape and a composite surface shape obtained by composing respective surface shapes of two main surfaces is 25 nm or less, is selected.

Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second mandrel structures having a first width is formed on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width less than the first width are formed on non-facing sidewall surfaces of the neighboring pair of first mandrel structures. Each first mandrel structure is removed and a spacer is formed on a sidewall surface of the first and second sets of second mandrel structures. In the region between the neighboring pair of first mandrel structure, a merged spacer is formed. The first and second sets of second mandrel structures are removed. A portion of an underlying substrate can be patterned utilizing each spacer and the merged spacer as etch masks.

In method of patterning a substrate, a first relief pattern is formed based on a first layer deposited over a substrate. Openings in the first relief pattern are filled with a reversal material. The first relief pattern is then removed from the substrate and the reversal material remains on the substrate to define a second relief pattern. A fill material is deposited over the substrate that is in contact with the second relief pattern, and sensitive to a photo-acid generated from a photo-acid generator in the second relief pattern. Selected portions of the second relief pattern are exposed to a first actinic radiation to generate the photo-acid in the selected portions of the second relief pattern. The photo-acid are driven from the selected portions of the second relief pattern into portions of the fill material so that the portions of the fill material to become soluble to a predetermined developer.

Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.

A first film having a repetitive line pattern is formed on an under film. A second film is formed on a side surface of the first film. The second film has an etching selectivity different from that of the first film. A third film is formed on an upper surface and a side surface of the second film. The third film has an etching selectivity different from those of the first and second films. A resist pattern with an opening is formed on the third film. A recess that exposes upper surfaces of the first, second and third films is formed by etching the third film by using the resist pattern as an etching mask. An upper surface of the under film is exposed by etching the first and third films. A through hole that penetrates through the under film is formed by etching the under film.

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a β line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a γ line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an α line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a βγβ jog; a βαβ jog; an αβγ jog; a γβα jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.