The present disclosure provides a thin film transistor, a method for producing the same, an array substrate and a display apparatus. An electrode of the thin film transistor is made of Cu or Cu alloy, and an anti-oxidization layer is used to prevent oxidization of Cu. The thin film transistor includes a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode and a drain electrode provided on a base substrate, wherein the gate electrode and/or the drain and source electrodes is/are made of Cu or Cu alloy. The thin film transistor further includes an anti-oxidization layer made of a topological insulator material, the anti-oxidization layer being provided above and in contact with the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy.

An electron device having a channel layer made of graphene is disclosed. The electron device includes a graphene layer on a substrate, and a source electrode, a drain electrode, and a gate insulating film on the graphene layer. The electron device further includes a first gate electrode on the gate insulating film between the source electrode and the drain electrode, and a second gate electrode within the substrate. For the second gate electrode, another gate insulating film is on the graphene layer, or alternatively, a part of the substrate is interposed between the second gate electrode and the channel layer.

A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.

Embodiments of the present disclosure describe multi-layer graphene assemblies including a layer of fluorinated graphene, dies and systems containing such structures, as well as methods of fabrication. The fluorinated graphene provides an insulating interface to other graphene layers while maintaining the desirable characteristics of the nonfluorinated graphene layers. The assemblies provide new options for utilizing graphene in integrated circuit devices and interfacing graphene with other materials. Other embodiments may be described and/or claimed.

A manufacturing method of a touch panel includes the steps of providing a substrate, forming a first conductive film on the substrate, forming a first mask on the first conductive film, etching the first conductive film to form electrode portions and lower intersect portions of the touch panel, forming an insulating film made of a negative resist on the first conductive film, and forming a contact hole above the electrode portion by removing the insulating film. The steps further include forming a second conductive film on the insulating film, forming a second mask on the second conductive film, etching the second conductive film to form an upper intersect portion connected between two adjacent electrode portions via the contact hole and intersecting with the lower intersect portion, and forming protective film on the second conductive film.

A field-effect transistor and a manufacturing method thereof are provided. The method includes depositing a first insulating layer on a substrate; forming a source electrode and a drain electrode on the first insulating layer; forming a carbon quantum dots active layer covering the source electrode and the drain electrode; and forming a second insulating layer and a gate electrode on the carbon quantum dots active layer sequentially. According to the above method, the present disclosure making the field-effect transistor active layer with carbon quantum dots as materials, which enriches the material of the field-effect transistor, reduces the environmental pollution in current technology by using metal dots film, and reduces the dependence on metal elements.

The present invention provides a TFT substrate manufacturing method, which includes first forming a graphene semiconductor active layer on a metal foil, then sequentially forming an inorganic insulation layer and an organic base on the graphene semiconductor active layer, followed by turning up-side down to set the metal foil on a topmost layer, then forming a photoresist layer, through a patterning operation, on the metal foil and subjecting the metal foil to etching to form a source electrode and a drain electrode, then sequentially forming an organic insulation layer and a gate electrode conductor layer on the photoresist layer and the graphene semiconductor active layer, and finally, applying a photoresist peeling agent to remove the photoresist layer with portions of the organic insulation layer and the gate electrode conductor layer located thereon removed therewith so as to obtain patterned gate insulation layer and gate electrode. The manufacturing method involves an operation of turning up-side down to to allow the metal foil that is used to deposit a graphene film to be re-used as an electrode material for formation of the source and drain electrodes so that an effect of lowering down manufacturing cost and simplifying operations can be achieved. And, through application of lift-off technique, only one mask is necessary to obtain patterned source electrode, drain electrode, and gate electrode.

A field-effect transistor and a manufacturing method thereof are provided. The method includes depositing a first insulating layer on a substrate; forming a source electrode and a drain electrode on the first insulating layer; forming a carbon quantum dots active layer covering the source electrode and the drain electrode; and forming a second insulating layer and a gate electrode on the carbon quantum dots active layer sequentially. According to the above method, the present disclosure making the field-effect transistor active layer with carbon quantum dots as materials, which enriches the material of the field-effect transistor, reduces the environmental pollution in current technology by using metal dots film, and reduces the dependence on metal elements.

The present invention provides a TFT substrate manufacturing method, which includes first forming a graphene semiconductor active layer on a metal foil, then sequentially forming an inorganic insulation layer and an organic base on the graphene semiconductor active layer, followed by turning up-side down to set the metal foil on a topmost layer, then forming a photoresist layer, through a patterning operation, on the metal foil and subjecting the metal foil to etching to form a source electrode and a drain electrode, then sequentially forming an organic insulation layer and a gate electrode conductor layer on the photoresist layer and the graphene semiconductor active layer, and finally, applying a photoresist peeling agent to remove the photoresist layer with portions of the organic insulation layer and the gate electrode conductor layer located thereon removed therewith so as to obtain patterned gate insulation layer and gate electrode. The manufacturing method involves an operation of turning up-side down to to allow the metal foil that is used to deposit a graphene film to be re-used as an electrode material for formation of the source and drain electrodes so that an effect of lowering down manufacturing cost and simplifying operations can be achieved. And, through application of lift-off technique, only one mask is necessary to obtain patterned source electrode, drain electrode, and gate electrode.

A vertical channel field-effect transistor is taught. The vertical channel field-effect transistor comprises a primary substrate and a secondary substrate. A bottom conducting layer is provided on the primary substrate. A top conducting layer is transferred from a secondary substrate to the primary substrate by using an insulating adhesive layer. The thickness of the insulating adhesive layer defines the channel length. The portion of the top conducting layer which is over the bottom conducting layer defines the maximum possible channel. At least one semiconducting layer is provided on and around a perimeter of at least a portion of the channel width. At least one insulating layer is provided on at least a portion of the at least one semiconducting layer. At least one gate conducting layer provided on at least a portion of the at least one insulating layer.