A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

Chemical mechanical polishing (CMP) compositions, systems and methods of using the compositions for polishing tungsten or tungsten-containing substrates. The compositions comprise nano-sized abrasive; metal compound coated organic polymer particles as solid state catalyst; oxidizer; tungsten corrosion inhibitor; and a water based liquid carrier.

A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one trim layer and at least one masking layer under the trim layer. The trim layer may have structures that have smaller linewidths than the structures of the patterned layer by utilizing an isotropic gaseous process to trim the structures of the trim layer. The structures of the trim layer, after trimming, may then be replicated in the mask layer to provide a linewidth in the mask layer that is smaller than the linewidth in the patterned layer. The technique may allow nanometer control of an EUV lithography process at pitches of 36 nm or less. In one embodiment, the technique may be utilized to provide an EUV lithography process for increasing the trench dimensions in a BEOL trench formation process step.

A semiconductor element is disclosed including a construction with electrode-dividing grooves, in which a dark current is smaller than in existing examples. A method of forming such grooves is also disclosed. In an embodiment, grooves, which electrically divide an electrode layer formed on the surface of a substrate, are formed with a V-shaped cross-sectional shape, groove side walls in the electrode layer, constituting the grooves, being sloping surfaces. An embodiment of the method of forming the grooves includes using a dicing blade having a blade distal end portion which is sharpened into a V-shape to cut a semiconductor wafer in which multiple patterns of semiconductor elements including an electrode layer on the surface of a substrate are formed, forming the grooves having a V-shaped cross-sectional shape which divide the electrode layer in each semiconductor element.

A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

A method of forming a semiconductor device including a memory cell area having a plurality of memory cells and a peripheral circuit area for reading and writing data on the memory cells in the memory cell area of a semiconductor substrate is provided. Contact pads are formed on source/drain regions of transistors in the peripheral circuit area as well as in the memory cell area. The contact pads are concurrently formed on the source/drain regions of the transistors in the memory cell area and the peripheral circuit area. As a result, there is no step difference between the contact pads and, thus, it is easy to form metal contact plugs on the contact pads.

A method of forming a semiconductor device including a memory cell area having a plurality of memory cells and a peripheral circuit area for reading and writing data on the memory cells in the memory cell area of a semiconductor substrate is provided. Contact pads are formed on source/drain regions of transistors in the peripheral circuit area as well as in the memory cell area. The contact pads are concurrently formed on the source/drain regions of the transistors in the memory cell area and the peripheral circuit area. As a result, there is no step difference between the contact pads and, thus, it is easy to form metal contact plugs on the contact pads.