H01L21/2205

SEMICONDUCTOR DEVICE SOURCE/DRAIN REGION WITH ARSENIC-CONTAINING BARRIER REGION

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

Method of manufacturing semiconductor devices by using epitaxy and semiconductor devices with a lateral structure

Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed.

SILICON CARBIDE SEMICONDUCTOR DEVICE
20190103462 · 2019-04-04 · ·

For example, a pin diode is constituted by a silicon carbide epitaxial substrate in which silicon carbide epitaxial layers constituting an n-type buffer region, an n.sup.-type drift region, and a p.sup.++-type anode region are sequentially formed by epitaxial growth on a front surface of an n.sup.+-type silicon carbide substrate. The n.sup.-type drift region has an n-type impurity concentration is, for example, about 110.sup.14/cm.sup.3 to 110.sup.16/cm.sup.3. The n.sup.-type drift region has a boron concentration that is substantially lower than an n-type impurity concentration of the n.sup.-type drift region and that, for example, is about 110.sup.14/cm.sup.3 or less. During epitaxial growth of the n.sup.-type drift region, automatic doping of boron to the n.sup.-type drift region is suppressed, whereby the boron concentration of the n.sup.-type drift region is reduced and the n.sup.-type drift region in which no traps are present is formed.

Doping Method
20190088482 · 2019-03-21 ·

A first dose of first dopants is introduced into a semiconductor body having a first surface. A thickness of the semiconductor body is increased by forming a first semiconductor layer on the first surface of the semiconductor body. While forming the first semiconductor layer a final dose of doping in the first semiconductor layer is predominantly set by introducing at least 20% of the first dopants from the semiconductor body into the first semiconductor layer.

Semiconductor substrate and manufacturing method of the same

Present disclosure provides a method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, including providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type, forming a polysilicon layer over the front surface, removing the polysilicon layer from the front surface, and depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature. A transition width of the dopant having the first conductivity type across the semiconductor wafer and the epitaxial layer is controlled by the predetermined temperature to be at least about 0.75 micrometer. A semiconductor device and a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer are also disclosed.

Field-effect transistor and method for the fabrication thereof

The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound semiconductor, wherein the compound semiconductor comprises at least one element from the chemical group III being selected from any of gallium, aluminum, indium and/or boron and wherein the compound semiconductor comprises at least one element from the chemical group V being selected from nitrogen, phosphorous and/or arsenic, wherein the compound semiconductor comprises at least nitrogen, wherein the field-effect transistor comprises at least any of a source electrode and/or a drain electrode, said source electrode and/or drain electrode comprising at least one doped region extending from the surface into the at least one layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm.

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME
20180308697 · 2018-10-25 ·

Present disclosure provides a method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, including providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type, forming a polysilicon layer over the front surface, removing the polysilicon layer from the front surface, and depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature. A transition width of the dopant having the first conductivity type across the semiconductor wafer and the epitaxial layer is controlled by the predetermined temperature to be at least about 0.75 micrometer. A semiconductor device and a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer are also disclosed.

DUAL CHANNEL FINFETS HAVING UNIFORM FIN HEIGHTS
20180240713 · 2018-08-23 ·

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

DUAL CHANNEL FINFETS HAVING UNIFORM FIN HEIGHTS
20180240714 · 2018-08-23 ·

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

Method of Manufacturing Semiconductor Devices by Using Epitaxy and Semiconductor Devices with a Lateral Structure

Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed.