SILICON CARBIDE SEMICONDUCTOR DEVICE

Abstract

For example, a pin diode is constituted by a silicon carbide epitaxial substrate in which silicon carbide epitaxial layers constituting an n-type buffer region, an n.sup.-type drift region, and a p.sup.++-type anode region are sequentially formed by epitaxial growth on a front surface of an n.sup.+-type silicon carbide substrate. The n.sup.-type drift region has an n-type impurity concentration is, for example, about 110.sup.14/cm.sup.3 to 110.sup.16/cm.sup.3. The n.sup.-type drift region has a boron concentration that is substantially lower than an n-type impurity concentration of the n.sup.-type drift region and that, for example, is about 110.sup.14/cm.sup.3 or less. During epitaxial growth of the n.sup.-type drift region, automatic doping of boron to the n.sup.-type drift region is suppressed, whereby the boron concentration of the n.sup.-type drift region is reduced and the n.sup.-type drift region in which no traps are present is formed.

Claims

1. A silicon carbide semiconductor device comprising: a semiconductor substrate of a first conductivity type and containing silicon carbide; a first semiconductor region provided on a surface of the semiconductor substrate and constituted by a silicon carbide crystal layer of the first conductivity type and having an impurity concentration lower than an impurity concentration of the semiconductor substrate; and a second semiconductor region of a second conductivity type provided on a first side of the first semiconductor region, opposite a second side of the first semiconductor region facing toward the semiconductor substrate, the second semiconductor region forming a pn junction with the first semiconductor region, wherein an impurity concentration of a first impurity of the first conductivity type of the first semiconductor region is at most 110.sup.16/cm.sup.3, and an impurity concentration of boron that is a second impurity different from the first impurity of the first conductivity type of the first semiconductor region is lower than the impurity concentration of the first impurity of the first conductivity type of the first semiconductor region and is at most 110.sup.14/cm.sup.3.

2. The silicon carbide semiconductor device according to claim 1, wherein the second semiconductor region, the first semiconductor region, and the semiconductor substrate constitute a diode.

3. The silicon carbide semiconductor device according to claim 1, wherein the second semiconductor region, the first semiconductor region, and the semiconductor substrate constitute a diode included in a bipolar device.

4. The silicon carbide semiconductor device according to claim 3, the bipolar device is any one of a bipolar transistor, an insulated gate bipolar transistor, and a thyristor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to an embodiment;

[0022] FIG. 2 is a characteristics diagram of simulation results of relationships between operating voltage during forward operation and current density;

[0023] FIG. 3 is a table of operating voltage values at a predetermined current density in FIG. 2; and

[0024] FIG. 4 is a cross-sectional view of a structure of a conventional silicon carbide semiconductor device.

DESCRIPTION OF EMBODIMENTS

[0025] First, problems associated with the conventional techniques will be described. In a device designed for high voltages and to have an n.sup.-type drift region that has a low impurity concentration, when other traps exist in the n.sup.-type drift region even when defects caused by carbon atom vacancies (Z.sub.1/2 center, etc.) are reduced, a problem arises in that the ON resistance characteristics degrade.

[0026] Embodiments of a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or , and represents one example. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described.

[0027] A structure of the silicon carbide semiconductor device according to the embodiment will be described. FIG. 1 is a cross-sectional view of the silicon carbide semiconductor device according to the embodiment. The silicon carbide semiconductor device according to the embodiment and depicted in FIG. 1, is for example, a silicon carbide (SiC) pin diode that uses a silicon carbide epitaxial substrate (semiconductor chip) 10. In a silicon carbide epitaxial substrate 10, silicon carbide epitaxial layers (silicon carbide crystal layers) constituting an n-type buffer region 2, an n.sup.-type drift region 3, and a p.sup.++-type anode region 4 are sequentially formed by epitaxial growth on a front surface of a starting substrate (n.sup.+-type silicon carbide substrate) 1 containing an n.sup.+-type silicon carbide.

[0028] The n.sup.+-type silicon carbide substrate 1 is an n.sup.+-type cathode region. The n.sup.+-type silicon carbide substrate 1 has an impurity concentration that may be, for example, about 110.sup.19/cm.sup.3. The n-type buffer region 2 is a dislocation conversion layer that suppresses propagation of stacking faults generated and originating from basal plane dislocations (BPDs) of the n.sup.+-type silicon carbide substrate 1, to the n.sup.-type drift region 3. The n-type buffer region 2 has function of converting with high efficiency, basal plane dislocations propagated to the n.sup.-type drift region 3 from the n.sup.+-type silicon carbide substrate 1 accompanying epitaxial growth, into threading edge dislocations that do not generate stacking faults. The n.sup.-type drift region 3 may be provided on the front surface of the n.sup.+-type silicon carbide substrate 1 without providing the n-type buffer region 2.

[0029] The n.sup.-type drift region 3 is a breakdown voltage region for sustaining a predetermined breakdown voltage of the silicon carbide semiconductor device and constitutes an intrinsic semiconductor layer (i-type: intrinsic) layer of a pin diode. The n.sup.-type drift region 3 has an n-type impurity concentration that is, for example, in a range from about 110.sup.14/cm.sup.3 to 110.sup.16/cm.sup.3. The n.sup.-type drift region 3 has an n-type impurity concentration and a thickness that varies according to the breakdown voltage and, for example, in a case of 1200V, are about 110.sup.16/cm.sup.3 or less and about 10 m or higher, respectively. Further, the n-type impurity concentration and the thickness of the n.sup.-type drift region 3, for example, in a case of 20 kV are 410.sup.14/cm.sup.3 or less and about 150 m or greater, respectively.

[0030] The n.sup.-type drift region 3, as described hereinafter, is formed in a state in which a measure is taken so that boron addition (automatic doping) during epitaxial growth is suppressed. A reason for this is that boron atoms present in the n.sup.-type drift region 3 are a factor that increases the ON resistance during forward operation. The ON resistance is element resistance at the time of forward current flow between the anode and cathode. In particular, a boron (B) concentration of the n.sup.-type drift region 3 is sufficiently lower than the n-type impurity concentration of the n.sup.-type drift region 3 and, for example, is about 110.sup.14/cm.sup.3 or less.

[0031] The p.sup.++-type anode region 4 may be a diffusion region formed by ion implantation in a surface layer (surface layer on a first side of the n.sup.-type drift region 3, opposite a second side thereof facing toward the n.sup.+-type silicon carbide substrate 1) on a front surface of the silicon carbide epitaxial substrate 10. The p.sup.++-type anode region 4 has an impurity concentration that is set sufficiently higher than an impurity concentration of the n.sup.-type drift region 3. In particular, the impurity concentration of the p.sup.++-type anode region 4 may be, for example, about 110.sup.16/cm.sup.3 or higher. The p.sup.++-type anode region 4 has a thickness that may be, for example, in a range of about 0.1 m to a few m.

[0032] The impurity concentration and the thickness of the p.sup.++-type anode region 4 is set so that decreases in the breakdown voltage due to punchthrough to a front electrode 5 does not occur. A reason for this is as follows. For example, when the impurity concentration of the p.sup.++-type anode region 4 is not sufficiently higher than that of the n.sup.-type drift region 3 and the thickness of the p.sup.++-type anode region 4 is thin, a depletion layer that spreads from a pn junction of the p.sup.++-type anode region 4 and the n.sup.-type drift region 3 during reverse operation may punchthrough to the front electrode 5 and the breakdown voltage may decrease.

[0033] The front electrode 5 is in contact with and electrically connected to the p.sup.++-type anode region 4. The front electrode 5 is an anode electrode. A rear electrode 6 is in contact with a rear surface (rear surface of the n.sup.+-type silicon carbide substrate 1) of the silicon carbide epitaxial substrate 10 and is electrically connected to the n.sup.+-type silicon carbide substrate 1 that is the n.sup.+-type cathode region. The rear electrode 6 is a cathode electrode. In FIG. 1, only an active region responsible for current driving is depicted and an edge termination region surrounding a periphery of the active region is not depicted. The edge termination region is a region that mitigates electric field toward a front surface of the silicon carbide epitaxial substrate 10 and sustains the breakdown voltage.

[0034] A method of manufacturing the silicon carbide semiconductor device according to the embodiment will be described. First, the n.sup.+-type silicon carbide substrate (support wafer) 1 is prepared, the n.sup.+-type silicon carbide substrate 1 is cleaned by a general semiconductor substrate cleaning method (organic cleaning method, RCA cleaning method, etc.). Next, the n.sup.+-type silicon carbide substrate 1 is inserted in an epitaxial growth furnace (chamber (not depicted)). Next, a source gas, a carrier gas, and a doping gas, etc. are introduced into the epitaxial growth furnace, and the silicon carbide epitaxial substrate (semiconductor wafer) 10 is fabricated in which silicon carbide epitaxial layers constituting the n-type buffer region 2, the n.sup.-type drift region 3, and the p.sup.++-type anode region 4 are sequentially formed by epitaxial growth.

[0035] At this time, as the source gas, a gas containing silicon (Si) and a gas containing carbon (C) are introduced. The gas containing silicon may be, for example, a monosilane (SiH.sub.4) gas. The gas containing carbon, for example, may be a propane (C.sub.3H.sub.8) gas. As the carrier gas, for example, a hydrogen (H.sub.2) gas may be used. As an n-type doping gas, for example, a phosphine (PH.sub.3) gas or an arsine (AsH.sub.3) gas may be used. As a p-type doping gas, for example, trimethylaluminum (Al(CH.sub.3).sub.3) gas may be used.

[0036] Further, during epitaxial growth of an n.sup.-type silicon carbide epitaxial layer constituting the n.sup.-type drift region 3, a measure for suppressing unintended boron addition (automatic doping) to the n.sup.-type silicon carbide epitaxial layer is taken. As a result, the n.sup.-type drift region 3 may be formed in which substantially no defects due to carbon atom vacancies (for example, electron traps such as Z.sub.1/2 centers, etc.) or hole traps (energy levels capturing holes) due to boron are present. Boron is a light element and automatic doping of boron to the n.sup.-type silicon carbide epitaxial layer cannot be avoided. Therefore, to suppress the addition of boron to the n.sup.-type drift region 3 during epitaxial growth, for example, one or more of the following measures is taken.

[0037] A first measure is use of a member (susceptor, quartz tube, etc.) having an ultrahigh purity (for example, a purity of about 6N(=99.9999%) or 9N (=99.9999999%)) and containing minimal boron to reduce the boron released in the atmosphere in the epitaxial growth furnace. A second measure is use of a gas having an ultrahigh purity and containing minimal boron, whereby boron included in the gas introduced in the epitaxial growth furnace is reduced. A third measure is sufficiently performing aging or preheat treatment (heat treatment), etc. in the epitaxial growth furnace to reduce the boron released from the member in the epitaxial growth furnace into the atmosphere.

[0038] After the n.sup.-type silicon carbide epitaxial layer constituting the n.sup.-type drift region 3 is formed by epitaxial growth, similar to a conventional method, carbon atoms may be supplied in the n.sup.-type drift region 3 and heat treatment may be performed to reduce in the n.sup.-type drift region 3, defects caused by carbon atom vacancies.

[0039] Next, by photolithography and etching, the p.sup.++-type silicon carbide epitaxial layer constituting the p.sup.++-type anode region 4 is selectively removed and in the edge termination region, the n.sup.-type drift region 3 is exposed at the front surface of the silicon carbide epitaxial substrate 10. When the p.sup.++-type anode region 4 is selectively formed by ion implantation, in the edge termination region, the n.sup.-type drift region 3 is already exposed at the front surface of the silicon carbide epitaxial substrate 10 and therefore, etching is not performed.

[0040] Next, in the edge termination region, for example, a breakdown voltage structure such as a guard ring, RESURF, etc. for mitigating the electric field strength in a lateral direction (direction parallel to the front surface of the silicon carbide epitaxial substrate 10) is formed. Next, on the front and rear surfaces of the silicon carbide epitaxial substrate 10, the front electrode 5 and the rear electrode 6 are formed respectively. Thereafter, the semiconductor wafer is diced (cut) into individual chip, whereby the pin diode depicted in FIG. 1 and including the n-type buffer region 2 is completed.

[0041] Operating voltage (forward voltage) during forward operation of the silicon carbide semiconductor device according to the embodiment was verified. FIG. 2 is a characteristics diagram of simulation results of relationships between operating voltage during forward operation and current density. FIG. 3 is a table of operating voltage values at a predetermined current density in FIG. 2. FIG. 3 depicts the operating voltages (forward voltage) when Example and comparison examples 1, 2 are forward operated at the same current density (=100 A/cm.sup.2).

[0042] Simulation results of the relationship between the forward voltage and current density of the pin diode (hereinafter, Example) including the silicon carbide semiconductor device according to the embodiment (refer to FIG. 1) are depicted in FIG. 2. Further, in FIG. 2, for comparison, simulations results of the relationship between the forward voltage and current density of a pin diode (hereinafter, comparison examples 1, 2) that includes the conventional silicon carbide semiconductor device (refer to FIG. 4) are depicted.

[0043] In Example, traps are substantially not present in the n.sup.-type drift region 3 (trap density in the n.sup.-type drift region 30/cm.sup.3). In comparison example 1, traps are introduced at a trap density of about 110.sup.11/cm.sup.3 in the n.sup.-type drift region (the silicon carbide epitaxial layer 103). In comparison example 2, traps are introduced at a trap density of about 110.sup.12/cm.sup.3 in the n.sup.-type drift region. Here, the traps are electron traps and hole traps. The breakdown voltage of Example and comparison examples 1, 2 was 13 kV.

[0044] The results depicted in FIG. 2 confirm that in Example and in comparison examples 1, 2, the higher is the current density, the greater the forward voltage increases. However, for Example, it was confirmed that increases in the forward voltage were suppressed compared to comparison examples 1, 2. For example, as depicted in FIG. 3, during operation at a current density of 100 A/cm.sup.2, the forward voltage of Example was 3.38V whereas the forward voltages of comparison examples 1, 2 were 5.74V and 16.67V, respectively.

[0045] In other words, in comparison examples 1, 2, the lower is the trap density in the n.sup.-type drift region, the amount of increase in the forward voltage with respect to the magnitude of the current density may be reduced. However, compared to Example, the amount of increase in the forward voltage is large and conduction loss is large. By establishing a state in which traps substantially are not present in the n.sup.-type drift region 3 like in Example, increases in the forward voltage may be suppressed and the conduction loss may be reduced.

[0046] As described, according to the embodiment, automatic doping of boron in the n.sup.-type drift region is suppressed, boron concentration in the n.sup.-type drift region is sufficiently lower than the n-type impurity concentration and, for example, may be is set to be about 110.sup.14/cm.sup.3 or less. In this manner, the boron concentration of the n.sup.-type drift region is extremely low, whereby hole traps caused by boron atoms are not introduced into the n.sup.-type drift region. Therefore, decreases of minority carriers (holes) in the n.sup.-type drift region during bipolar operation (during forward operation of the diode) may be suppressed. In addition, during bipolar operation, indirect recombination of electrons due to hole traps is suppressed and decreases in majority carriers (electrons) of the n.sup.-type drift region may be suppressed. In other words, during bipolar operation, decreases of the carrier concentration of the n.sup.-type drift region may be suppressed and the conduction resistance (ON resistance) may be reduced. Therefore, low ON resistance characteristics close to ideal characteristics based on characteristics for silicon carbide as the semiconductor material may be obtained. Further, according to the embodiment, adverse effects of the hole traps during high-temperature operation decrease and therefore, compared to low-temperature operation, negative temperature characteristics of the ON resistance during high-temperature operation becoming smaller are improved.

[0047] Further, according to the embodiment, when forward current of a current density equal to that of a conventional structure flows, the forward voltage at the time of bipolar operation may be reduced more than that with the conventional structure and the conduction loss may be reduced. Therefore, a silicon carbide semiconductor device capable of bipolar operation at a high current density in a state in which the ON resistance is maintained may be provided.

[0048] In the embodiments of the present invention, various modifications within a range not departing from the spirit of the invention are possible. For example, dimensions, impurity concentrations, etc. of regions may be variously set according to required specifications. Further, the present invention is applicable to parasitic pin diodes built in unipolar devices such as metal oxide semiconductor field effect transistors (MOSFETs). Further, the present invention is applicable to bipolar transistors, insulated gate bipolar transistors (IGBTs), bipolar devices such as thyristors, etc.

[0049] The silicon carbide semiconductor device according to the embodiments of the present invention achieves an effect in that decreases in the carrier concentration of the n.sup.-type drift region may be suppressed and therefore, the ON resistance characteristics during bipolar operation (during forward operation of the diode) may be improved.

[0050] As described, the silicon carbide semiconductor device according to the embodiments of the present invention is useful for high-voltage (about 1200V or higher) silicon carbide semiconductor devices and is particularly suitable for bipolar silicon carbide semiconductor devices.

[0051] Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.