A method of manufacturing a semiconductor device, including preparing a semiconductor substrate having a main surface, forming a device element structure on the main surface, forming a protective film on the main surface of the semiconductor substrate to protect the device element structure, the protective film having an opening therein, forming at least one material film in a predetermined pattern on the main surface of the semiconductor substrate and in the opening of the protective film, the at least one material film being separate from the protective film by a distance of less than 1 mm, forming a resist film on the main surface of the semiconductor substrate, covering the protective film and the at least one material film, the resist film having an opening therein corresponding to an inducing region for impurity defects, and inducing the impurity defects in the semiconductor substrate, using the resist film as a mask.

A method of processing and passivating an implanted workpiece is disclosed, wherein, after passivation, the fugitive emissions of the workpiece are reduced to acceptably low levels. This may be especially beneficial when phosphorus, arsine, germane or another toxic species is the dopant being implanted into the workpiece. In one embodiment, a sputtering process is performed after the implantation process. This sputtering process is used to sputter the dopant at the surface of the workpiece, effectively lowering the dopant concentration at the top surface of the workpiece. In another embodiment, a chemical etching process is performed to lower the dopant concentration at the top surface. After this sputtering or chemical etching process, a traditional passivation process can be performed.

Examples of a shower plate include a body part of a plate-like conductor having a plurality of through holes, the body part being provided with a surface treated part on at least a part of a lower surface, the surface treated part having been subjected to surface treatment, thereby causing two or more regions having different emissivities to exist on the lower surface, and a flange surrounding the body part.

Examples of a shower plate include a body part of a plate-like conductor having a plurality of through holes, the body part being provided with a surface treated part on at least a part of a lower surface, the surface treated part having been subjected to surface treatment, thereby causing two or more regions having different emissivities to exist on the lower surface, and a flange surrounding the body part.

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.

A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.

A reaction apparatus contacts a process gas on a semiconductor wafer during a wafering process. The semiconductor wafer defines a center region. The reaction apparatus includes an upper dome, a lower dome, a shaft, and a cap. The lower dome is attached to the upper dome, and the upper dome and the lower dome define a reaction chamber. The cap is positioned on the shaft within the reaction chamber for reducing heat absorbed by the center region of the semiconductor wafer. The cap is attached to a first end of the shaft. The cap includes a tube and a disc. The tube defines a tube diameter larger than a shaft diameter of the shaft. The tube circumscribes the first end of the shaft. The disc is attached to the tube and is positioned to block radiant heat from heating the center region of the semiconductor wafer.

A grid assembly for injecting process gas to a chamber. The grid assembly including a gas inlet for delivering the process gas to the grid assembly, a plurality of nozzles extending vertically through at least a portion of the grid assembly, and a plurality of layers in a vertical stacked arrangement. The plurality of layers including a top layer including one or more internal gas injection channels configured to receive process gas from the gas inlet, a bottom layer including a plurality of internal gas injection channels having one or more injection apertures configured to deliver the process gas about a horizontal plane to one or more of the plurality of nozzles, and one or more sublayers disposed between the top layer and the bottom layer, each of the one or more sublayers including an increasing number of internal gas injection channels as the one or more sublayers advance from the top layer to the bottom layer. Plasma processing apparatuses and method of processing workpiece are also provided.