A method of processing includes directing an electron beam comprising ballistic electrons from an electron source towards a peripheral region of a substrate to be processed. The peripheral region surrounds a central region of the substrate. The electron beam may be directed such that the ballistic electrons impinge on the peripheral region and not on the central region of the substrate. The ballistic electrons may stimulate chemical reactions on the substrate. The method may include placing the substrate on a substrate holder disposed within a vacuum chamber. The method may also include generating the electron beam from a plasma in the vacuum chamber. The method may further include processing the substrate with ions from the plasma.

A method of processing includes directing an electron beam comprising ballistic electrons from an electron source towards a peripheral region of a substrate to be processed. The peripheral region surrounds a central region of the substrate. The electron beam may be directed such that the ballistic electrons impinge on the peripheral region and not on the central region of the substrate. The ballistic electrons may stimulate chemical reactions on the substrate. The method may include placing the substrate on a substrate holder disposed within a vacuum chamber. The method may also include generating the electron beam from a plasma in the vacuum chamber. The method may further include processing the substrate with ions from the plasma.

A method of processing and passivating an implanted workpiece is disclosed, wherein, after passivation, the fugitive emissions of the workpiece are reduced to acceptably low levels. This may be especially beneficial when phosphorus, arsine, germane or another toxic species is the dopant being implanted into the workpiece. In one embodiment, a sputtering process is performed after the implantation process. This sputtering process is used to sputter the dopant at the surface of the workpiece, effectively lowering the dopant concentration at the top surface of the workpiece. In another embodiment, a chemical etching process is performed to lower the dopant concentration at the top surface. After this sputtering or chemical etching process, a traditional passivation process can be performed.

Provided is a method of manufacturing a semiconductor structure. The method includes: providing a substrate, where the substrate includes a plurality of component areas and peripheral areas surrounding the plurality of component areas; next, forming a sacrificial layer on each of the plurality of component areas, and forming a semiconductor active layer on the sacrificial layer and the substrate not covered with the sacrificial layer; patterning the semiconductor active layer to remove the semiconductor active layer on the peripheral areas so as to form a plurality of annular grooves which expose the sacrificial layer, such that the semiconductor active layer on each of the plurality of component areas is independent; afterwards, removing the sacrificial layer on each of the plurality of component areas through the annular grooves, such that the independent semiconductor active layer is separated from the substrate, where the independent semiconductor active layer forms a semiconductor structure.

Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.

A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

The present disclosure provides a processing method for semiconductor surface defects and a preparation method for semiconductor devices. The processing method for semiconductor surface defects includes: placing a semiconductor device in a plasma processing device, the semiconductor device comprising a semiconductor substrate and deposition layers formed on the surface of the semiconductor substrate, bubbles being formed in the deposition layers; and plasma bombarding the surface of the deposition layer to break the bubbles, so that the surface of the deposition layer is flat.

The present disclosure provides a processing method for semiconductor surface defects and a preparation method for semiconductor devices. The processing method for semiconductor surface defects includes: placing a semiconductor device in a plasma processing device, the semiconductor device comprising a semiconductor substrate and deposition layers formed on the surface of the semiconductor substrate, bubbles being formed in the deposition layers; and plasma bombarding the surface of the deposition layer to break the bubbles, so that the surface of the deposition layer is flat.

A semiconductor wafer to be treated is heated at a first preheating temperature ranging from 100 to 200° C. while a pressure in a chamber housing the semiconductor wafer is reduced to a pressure lower than an atmospheric pressure. After the semiconductor wafer is preheated to increase the temperature into a second preheating temperature ranging from 500 to 700° C. while the pressure in the chamber is restored to a pressure higher than the reduced pressure, a flash lamp emits a flashlight to a surface of the semiconductor wafer. Heating the semiconductor wafer at the first preheating temperature that is a relatively low temperature enables, for example, the moisture absorbed on the surface of the semiconductor wafer in trace amounts to be desorbed from the surface, and also enables the flash heating treatment to be performed with oxygen derived from such absorption removed as much as possible.