A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

A dielectric layer is formed on a silicon substrate. A liner layer is formed on the dielectric layer. A conductive metal layer is formed on the liner layer. A first sputter etching operation is performed on the conductive metal layer, wherein the first sputter etching operation uses a first type of etch chemistry configured to subtractively pattern the conductive metal layer for a first etching time period resulting in the remaining conductive metal layer having respective sidewalls that are not substantially vertical. A second sputter etching operation is performed on the remaining conductive metal layer, wherein the second sputter etching operation uses a second type of etch chemistry configured to further subtractively pattern the remaining conductive metal layer for a second etching time period resulting in the remaining conductive metal layer having respective sidewalls that are substantially vertical. The conductive metal layer remaining after the second sputter etching operation comprises a metal interconnect.

The present invention relates to a method for manufacturing a nonvolatile memory thin film device by using a neutral particle beam generation apparatus. The present invention solves the problem that substrates such as glass and a plastic film may not be used for manufacturing the memory thin film device due to the high temperature heat treatment process for a long time, in the existing method for manufacturing the thin film device having the nonvolatile memory function by forming the mobile proton layer.

The present invention relates to a method for manufacturing a nonvolatile memory thin film device by using a neutral particle beam generation apparatus. The present invention solves the problem that substrates such as glass and a plastic film may not be used for manufacturing the memory thin film device due to the high temperature heat treatment process for a long time, in the existing method for manufacturing the thin film device having the nonvolatile memory function by forming the mobile proton layer.

A semiconductor device includes: a first conductivity type drift region having crystal defects generated by electron-beam irradiation; a first main electrode region of a first conductivity type arranged in the drift region and having an impurity concentration higher than that of the drift region; and a second main electrode region of a second conductivity type arranged in the drift region to be separated from the first main electrode region, wherein the crystal defects contain a first composite defect implemented by a vacancy and oxygen and a second composite defect implemented by carbon and oxygen, and a density of the crystal defects is set so that a peak signal intensity of a level of the first composite defect identified by a deep-level transient spectroscopy measurement is five times or more than a peak signal intensity of a level of the second composite defect.

A semiconductor device includes: a first conductivity type drift region having crystal defects generated by electron-beam irradiation; a first main electrode region of a first conductivity type arranged in the drift region and having an impurity concentration higher than that of the drift region; and a second main electrode region of a second conductivity type arranged in the drift region to be separated from the first main electrode region, wherein the crystal defects contain a first composite defect implemented by a vacancy and oxygen and a second composite defect implemented by carbon and oxygen, and a density of the crystal defects is set so that a peak signal intensity of a level of the first composite defect identified by a deep-level transient spectroscopy measurement is five times or more than a peak signal intensity of a level of the second composite defect.

A manufacturing method of a monocrystalline silicon includes: a growth step in which a seed crystal having contacted a silicon melt is pulled up and a crucible is rotated and raised to form a straight body of the monocrystalline silicon; a separating step in which the monocrystalline silicon is separated from the silicon melt; a state holding step in which the crucible and the monocrystalline silicon are lowered and the monocrystalline silicon is kept at a level at which an upper end of the straight body is located at the same level as an upper end of a heat shield or is located below the upper end of the heat shield for a predetermined time; and a draw-out step in which the monocrystalline silicon is drawn out of a chamber.

A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C., and forming a first load terminal structure at the first side of the semiconductor body.

A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C., and forming a first load terminal structure at the first side of the semiconductor body.

An insulated gate bipolar transistor (IGBT) includes: a p base layer disposed close to a front surface of an n-type silicon substrate; and a deep n.sup.+ buffer layer and a shallow n.sup.+ buffer layer disposed close to a back surface of the n-type silicon substrate. The p base layer has a higher impurity concentration than the n-type silicon substrate. The deep n.sup.+ buffer layer and shallow n.sup.+ buffer layer have higher impurity concentrations than the n-type silicon substrate. The deep n.sup.+ buffer layer is disposed throughout a region close to the back surface in the n-type silicon substrate. The shallow n.sup.+ buffer layer is selectively disposed close to the back surface in the n-type silicon substrate. The shallow n.sup.+ buffer layer has a higher impurity concentration than the deep n.sup.+ buffer layer, and is shallower from the back surface than the deep n.sup.+ buffer layer.