A method for fabricating a thin film transistor includes providing a substrate (100); forming a semiconductor layer (105) over the substrate (100); forming a source-drain metal layer (106) over the semiconductor layer (105); applying one patterning process to the semiconductor layer (105) and the source-drain metal layer (106) to form an active layer (1), a source electrode (2), and a drain electrode (3); forming a gate insulating layer (101) and an interlayer insulating layer (102) that cover the active layer (1), the source electrode (2), and the drain electrode (3); applying a patterning process to the interlayer insulating layer (102) to form a first window (10) in the interlayer insulating layer (102) to expose a portion of the gate insulating layer (101); and forming a gate electrode (4) in the first window (10). An orthogonal projection of the gate electrode (4) on the substrate (100) is in an orthogonal projection of the active layer (1) on the substrate (100).

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.

A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F.sub.2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1?10.sup.17 atoms/cm.sup.3.

The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume. The substrate includes a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method includes forming a silicon-containing layer over the channel structure to a hydrogen-or-deuterium plasma in the first processing volume at a flow rate of about 10 sccm to about 5000 sccm. The substrate is maintained at a temperature of about 100 C. to about 1100 C. during the exposing, the exposing forming a nucleated substrate. Subsequent to the exposing a thermal anneal operation is performed on the substrate.

Protons are injected from a back surface side of a semiconductor substrate to repair both defects within the semiconductor substrate and also defects in a channel forming region on a front surface side of the semiconductor substrate. As a result, variation in gate threshold voltage is reduced and leak current when a reverse voltage is applied is reduced. Provided is a semiconductor device including a semiconductor substrate that includes an n-type impurity region containing protons, on a back surface side thereof; and a barrier metal that has an effect of shielding from protons, on a front surface side of the semiconductor substrate.

A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.

A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.