Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor layer within or on a portion of a substrate, wherein the semiconductor layer includes a first type of semiconductor material. A gate stack is formed over a first exposed surface of the semiconductor layer. A first hydrogenated and doped semiconductor layer is formed over a second exposed surface of the semiconductor layer. A second hydrogenated and doped semiconductor layer is formed over a third exposed surface of the semiconductor layer, wherein a lateral dimension of the first hydrogenated and doped semiconductor layer terminates at a first sidewall of the gate stack, and wherein a lateral dimension of the second hydrogenated and doped semiconductor layer terminates at a second sidewall of the gate stack.

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor layer within or on a portion of a substrate, wherein the semiconductor layer includes a first type of semiconductor material. A gate stack is formed over a first exposed surface of the semiconductor layer. A first hydrogenated and doped semiconductor layer is formed over a second exposed surface of the semiconductor layer. A second hydrogenated and doped semiconductor layer is formed over a third exposed surface of the semiconductor layer, wherein a lateral dimension of the first hydrogenated and doped semiconductor layer terminates at a first sidewall of the gate stack, and wherein a lateral dimension of the second hydrogenated and doped semiconductor layer terminates at a second sidewall of the gate stack.

A semiconductor device includes a gate electrode extending in a first direction on a substrate, a first active pattern extending in a second direction intersecting the first direction on the substrate to penetrate the gate electrode, the first active pattern including germanium, an epitaxial pattern on a side wall of the gate electrode, a first semiconductor oxide layer between the first active pattern and the gate electrode, and including a first semiconductor material, and a second semiconductor oxide layer between the gate electrode and the epitaxial pattern, and including a second semiconductor material. A concentration of germanium of the first semiconductor material may be less than a concentration of germanium of the first active pattern, and the concentration of germanium of the first semiconductor material may be different from a concentration of germanium of the second semiconductor material.

The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

The present disclosure relates to an array substrate, a method for fabricating the same, a display panel, and a method for fabricating the same. The array substrate includes a substrate, an active layer on the substrate, a first insulating layer on the active layer, a gate electrode and a first electrode on the first insulating layer, wherein a projection of the first electrode on the substrate and a projection of the active layer on the substrate do not overlap, a third insulating layer on the first electrode, a projection of the third insulating layer on the substrate does not overlap with a projection of the active layer on the substrate, a second electrode on the third insulating layer, and a second insulating layer on the gate electrode and the second electrode.

Hydrogen annealing for heating a semiconductor wafer on which a thin film containing a dopant is deposited to an annealing temperature under an atmosphere containing hydrogen is performed. A native oxide film is inevitably formed between the thin film containing the dopant and the semiconductor wafer, however, by performing hydrogen annealing, the dopant atoms diffuse relatively easily in the native oxide film and accumulate at the interface between the front surface of the semiconductor wafer and the native oxide film. Subsequently, the semiconductor wafer is preheated to a preheating temperature under a nitrogen atmosphere, and then, flash heating treatment in which the front surface of the semiconductor wafer is heated to a peak temperature for less than one second is performed. The dopant atoms are diffused and activated in a shallow manner from the front surface of the semiconductor wafer, thus, the low-resistance and extremely shallow junction is obtained.

One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.

A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.

One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.

The present disclosure relates to an array substrate, manufacturing method thereof and display device using the same. The method for manufacturing the array substrate includes: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in one deposition process; and processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer. Through the above-mentioned method, the present disclosure can solve the problem of affecting the concentration of current carriers that caused by the oxidation of the surface of polysilicon, and improve the performance of the array substrate.