Method for selectively oxidizing the dielectric surface of a substrate surface comprising a dielectric surface and a metal surface are discussed. Method for cleaning a substrate surface comprising a dielectric surface and a metal surface are also discussed. The disclosed methods oxidize the dielectric surface and/or clean the substrate surface using a plasma generated from hydrogen gas and oxygen gas. The disclosed method may be performed in a single step without the use of separate competing oxidation and reduction reactions. The disclosed methods may be performed at a constant temperature and/or within a single processing chamber.

An embodiment of the present invention provides a method of fabricating a semiconductor device capable of relieving a dangling bond. The semiconductor device comprises a device isolation layer defining a plurality of active regions in a substrate, the device isolation layer including a first region where the active regions are spaced apart from each other at a first interval along a first direction and a second region where the active regions are spaced apart from each other at a second interval along the first direction, the second interval being wider than the first interval; a gate trench extending in the first direction to cross the active regions and the device isolation layer; and a buried gate structure gap-filling the gate trench, wherein a portion of the device isolation layer includes an air gap acting as a hydrogen pocket in a lower portion.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a dielectric stack over a substrate, forming a functional layer and a semiconductor channel through the dielectric stack, forming a conductor/insulator stack based on the dielectric stack, and forming memory cells through the conductor/insulator stack. Each memory cell includes a portion of the functional layer and the semiconductor channel. At least one of the functional layer and the semiconductor channel includes a certain amount of deuterium elements.

In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.

The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume. The substrate includes a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method includes forming a silicon-containing layer over the channel structure to a hydrogen-or-deuterium plasma in the first processing volume at a flow rate of about 10 sccm to about 5000 sccm. The substrate is maintained at a temperature of about 100° C. to about 1100° C. during the exposing, the exposing forming a nucleated substrate. Subsequent to the exposing a thermal anneal operation is performed on the substrate.

A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.

A semiconductor device includes a semiconductor layer, a crystal defect region formed in the semiconductor layer, and an insulating layer formed on the semiconductor layer, composed of an insulator containing silicon, and including, in the insulator, an Si—H bond in which a dangling bond of silicon atom is hydrogen-terminated.

In one embodiment, a semiconductor manufacturing apparatus includes a substrate processor configured to process a substrate with a gas of a first substance and a gas of a second substance, and discharge a first gas including the first substance and/or the second substance. The apparatus further includes a disposer configured to discard the first gas discharged from the substrate processor. The apparatus further includes a recoverer configured to generate a second gas including the second substance by using the first substance in the first gas discharged from the substrate processor, and supply the second gas to the substrate processor.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.