The present invention is a method for manufacturing a bonded SOI wafer, including: preparing, as a base wafer, a silicon single crystal wafer whose initial interstitial oxygen concentration is 15 ppma or more ('79ASTM); forming a silicon oxide film on a surface of the base wafer by heating the base wafer in an oxidizing atmosphere such that a feeding temperature at which the base wafer is fed into a heat treatment furnace for the heat treatment is 800° C. or more, and the base wafer is heated at the feeding temperature or higher; bonding the base wafer to the bond wafer with the silicon oxide film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a method for manufacturing a bonded SOI wafer by a base oxidation method which suppresses the formation of oxide precipitates in a base wafer while suppressing slip dislocation.

A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.

A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.

A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.

Disclosed herein is a method of forming a gettering layer for capturing metallic ions on the back side of a semiconductor wafer formed with devices on the face side thereof. The method includes irradiating the back-side surface of the semiconductor wafer with a pulsed laser beam having a pulse width corresponding to a thermal diffusion length of 10 to 230 nm, to thereby form the gettering layer.

Disclosed herein is a method of forming a gettering layer for capturing metallic ions on the back side of a semiconductor wafer formed with devices on the face side thereof. The method includes irradiating the back-side surface of the semiconductor wafer with a pulsed laser beam having a pulse width corresponding to a thermal diffusion length of 10 to 230 nm, to thereby form the gettering layer.

A super junction semiconductor device includes a semiconductor portion with first and second surfaces parallel to one another and including a doped layer of a first conductivity type formed at least in a cell area. Columnar first super junction regions of a second conductivity type extend in a direction perpendicular to the first surface and are separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A first electrode structure directly adjoins the first surface and a second electrode structure directly adjoins the second surface. The first electrode structure has a first thickness and the second electrode structure has a second thickness. A sum of the first and second thicknesses is at least 20% of the thickness of the semiconductor portion between the first and second surfaces.

A method of fabricating a solar cell can include forming a dielectric region on a silicon substrate. The method can also include forming an emitter region over the dielectric region and forming a dopant region on a surface of the silicon substrate. In an embodiment, the method can include heating the silicon substrate at a temperature above 900 degrees Celsius to getter impurities to the emitter region and drive dopants from the dopant region to a portion of the silicon substrate.

Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region.

Isotropic silicon and silicon-germanium etching with tunable selectivity is described. The method includes receiving a substrate having a layer of silicon and a layer of silicon-germanium with sidewall surfaces of silicon and silicon-germanium being uncovered, positioning the substrate in a processing chamber configured for etching substrates, and modifying uncovered surfaces of silicon and silicon-germanium by exposing the uncovered surfaces of silicon and silicon-germanium to radical species. The method further includes executing a gaseous chemical oxide removal process that includes flowing a mixture of a nitrogen-containing gas and a fluorine-containing gas at a first substrate temperature to form a fluorine byproduct followed by executing a sublimation process to remove the fluorine byproduct at a second substrate temperature that is higher than the first substrate temperature, and controlling the second substrate temperature to tune the sublimation rate and etch selectivity of a silicon oxide material relative to a silicon-germanium oxide material.