Patent classifications
H01L21/326
Methods of thinning and structuring semiconductor wafers by electrical discharge machining
A method of structuring and/or thinning a semiconductor wafer having a plurality of functional chip sites includes forming one or more semiconductor devices in a device region of each functional chip site at a frontside of the semiconductor wafer, and forming an electrode at one of the frontside or a backside of the semiconductor wafer. The side of the semiconductor wafer at which the electrode is formed is structured by applying voltage pulses between the electrode and a tool electrode positioned above the semiconductor wafer as part of an electrical discharge machining (EDM) process before the electrode is removed by the EDM process, and between the tool electrode and an intrinsic conductive layer formed on the side of the semiconductor wafer being structured after the electrode is removed by the EDM process.
Semiconductor devices having a plurality of unit cell transistors that have smoothed turn-on behavior and improved linearity
A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
Semiconductor devices having a plurality of unit cell transistors that have smoothed turn-on behavior and improved linearity
A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
SEMICONDUCTOR DEVICE WITH ADHESION LAYER AND METHOD OF MAKING
A method of making a semiconductor device includes forming an opening in a dielectric layer. The method further includes depositing a barrier layer in the opening. The method further includes depositing an adhesion layer over the barrier layer. The method further includes treating the adhesion layer using a hydrogen-containing plasma.
SEMICONDUCTOR DEVICE WITH ADHESION LAYER AND METHOD OF MAKING
A method of making a semiconductor device includes forming an opening in a dielectric layer. The method further includes depositing a barrier layer in the opening. The method further includes depositing an adhesion layer over the barrier layer. The method further includes treating the adhesion layer using a hydrogen-containing plasma.
SEMICONDUCTOR DEVICE WITH ADHESION LAYER
A gate structure includes a gate dielectric layer over a semiconductor workpiece. The gate structure further includes a work function layer over the gate dielectric layer, wherein the work function layer has a U-shape profile. The gate structure further includes an adhesion layer over the work function layer, wherein a surface of the adhesion layer farthest from the work function layer is substantially free of oxygen atoms. The gate structure further includes a conductive layer over the adhesion layer, wherein the conductive layer has an I-shape profile.
SEMICONDUCTOR DEVICE WITH ADHESION LAYER
A gate structure includes a gate dielectric layer over a semiconductor workpiece. The gate structure further includes a work function layer over the gate dielectric layer, wherein the work function layer has a U-shape profile. The gate structure further includes an adhesion layer over the work function layer, wherein a surface of the adhesion layer farthest from the work function layer is substantially free of oxygen atoms. The gate structure further includes a conductive layer over the adhesion layer, wherein the conductive layer has an I-shape profile.
Temperature control in RF chamber with heater and air amplifier
Systems, methods, and computer programs are presented for controlling the temperature of a window in a semiconductor manufacturing chamber. One apparatus includes a heater for receiving and heating a flow of air and an air amplifier coupled to pressurized gas. The air amplifier has an input that receives the flow of air from the heater, and the air amplifier having an output. A duct is coupled to the output of the air amplifier and a plenum is coupled to the duct. The plenum receives the flow of air and distributes the flow of air over a window of a plasma chamber. A temperature sensor is situated about the window of the plasma chamber and a controller is provided to control the air amplifier and the heater based on a temperature measured by the temperature sensor.
Radical generator and molecular beam epitaxy apparatus
A molecular beam epitaxy apparatus includes a radical generator for generating a radical species, a molecular beam cell for generating a molecular beam or an atomic beam, and a vacuum chamber for accommodating a substrate therein, in use, the substrate being irradiated with the radical species and the molecular beam or the atomic beam in vacuum, to thereby form, on the substrate, a crystal of a compound derived from the element of the radical species and the element of the molecular beam or the atomic beam.
Inductively coupled plasma apparatus
Methods and apparatus for plasma processing are provided herein. In some embodiments, a plasma processing apparatus includes a process chamber having an interior processing volume; a first RF coil disposed proximate the process chamber to couple RF energy into the processing volume; and a second RF coil disposed proximate the process chamber to couple RF energy into the processing volume, the second RF coil disposed coaxially with respect to the first RF coil, wherein the first and second RF coils are configured such that RF current flowing through the first RF coil is out of phase with RF current flowing through the RF second coil.