Microelectronic devices may include an active surface and a side surface. The side surface may include a first portion having a reflective surface and a second portion having a non-reflective surface. The reflective surface may be formed by depositing a conductive material in trenches formed in material of the wafer along streets between the microelectronic devices on a wafer. The conductive material may be heated. The wafer may be cooled after the conductive material is heated fracturing the wafer along the streets and separating the microelectronic devices.

Microelectronic devices may include an active surface and a side surface. The side surface may include a first portion having a reflective surface and a second portion having a non-reflective surface. The reflective surface may be formed by depositing a conductive material in trenches formed in material of the wafer along streets between the microelectronic devices on a wafer. The conductive material may be heated. The wafer may be cooled after the conductive material is heated fracturing the wafer along the streets and separating the microelectronic devices.

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed.

A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.

Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.

Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.

A plasma etching method is provided to perform a desired etching by switching a process condition while maintaining plasma by supplying high frequency power. A first plasma etching process is performed based on a first process condition. A second plasma etching process different from the first process conditions is performed based on a second process condition while supplying first high frequency power having first effective power. Second high frequency power having second effective power is intermittently supplied between the first plasma etching process and the second plasma etching process during a switch from the first plasma etching process to the second plasma etching process. The second effective power of the second high frequency power is equal to or lower than the first effective power of the first high frequency power in the second plasma etching process.

Apparatus and associate methods relate to a high-voltage MOSFET bounded by two trenches, each having dielectric sidewalls and a dielectric bottom isolating a top field plate and a bottom field plate. The top field plate is electrically connected to a biasing circuit net, and the bottom field plate is biased via a capacitive coupling to the top field plate. The upper field plate and lower field plate are configured to deplete the majority carriers in a drain region of the MOSFET bounded by the two trenches so as to equalize two local maxima of an electric field induced by a drain/body bias, the two local maxima located proximate a drain/body metallurgical junction and proximate a trench bottom. The two local maxima of the electric field are equalized by controlling a depth location of an intervening dielectric between the upper field plate and the lower field plate.