A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 μm to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.

A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 μm to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.

A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.

Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.

A system for zapping a wafer, the system may include a pulse generation unit that is configured to generate (a) first zapping pulses for causing a breakdown in a first location of a backside insulating layer of a wafer, and (b) second zapping pulses for causing a breakdown in a second location of the backside insulating layer of the wafer; a first conductive interface that is configured to convey the first zapping pulses to the first location, while contacting the first location; a second conductive interface that is configured to convey the second zapping pulses to the second location, while contacting the second location; and wherein the first location differs from the second location.

A system for zapping a wafer, the system may include a pulse generation unit that is configured to generate (a) first zapping pulses for causing a breakdown in a first location of a backside insulating layer of a wafer, and (b) second zapping pulses for causing a breakdown in a second location of the backside insulating layer of the wafer; a first conductive interface that is configured to convey the first zapping pulses to the first location, while contacting the first location; a second conductive interface that is configured to convey the second zapping pulses to the second location, while contacting the second location; and wherein the first location differs from the second location.

A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.

A method of making a semiconductor device includes forming an opening in a dielectric layer. The method further includes depositing a barrier layer in the opening. The method further includes depositing an adhesion layer over the barrier layer. The method further includes treating the adhesion layer using a hydrogen-containing plasma.